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soc/intel/tigerlake: Configure RP setting 

Add LTR and AER configuration to the root ports config.

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-04-07 20:45:28 -07:00 committed by Patrick Georgi
parent ba41ee1f0a
commit 5943117647
2 changed files with 11 additions and 2 deletions
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6
src/soc/intel/tigerlake/chip.h
View File

@ -118,6 +118,12 @@ struct soc_intel_tigerlake_config {
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
/* SMBus */
uint8_t SmbusEnable;

7
src/soc/intel/tigerlake/fsp_params.c
View File

@ -122,10 +122,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* RP Configs */
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
params->PcieRpL1Substates[i] =
get_l1_substate_control(config->PcieRpL1Substates[i]);
params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i];
}
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
if (dev) {