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soc/intel/broadwell: Use common early SPI code 

Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-06-21 18:08:53 +02:00
parent 4c7ef81a23
commit 5403423656
1 changed files with 2 additions and 13 deletions
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15
src/soc/intel/broadwell/bootblock/pch.c
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@ -10,18 +10,7 @@
#include <reg_script.h> #include <reg_script.h>
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <southbridge/intel/common/early_spi.h>
/*
* Enable Prefetching and Caching.
*/
static void enable_spi_prefetch(void)
{
u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
}
static void map_rcba(void) static void map_rcba(void)
{ {
@ -105,7 +94,7 @@ static void pch_early_lpc(void)
void bootblock_early_southbridge_init(void) void bootblock_early_southbridge_init(void)
{ {
map_rcba(); map_rcba();
enable_spi_prefetch(); enable_spi_prefetching_and_caching();
enable_port80_on_lpc(); enable_port80_on_lpc();
set_spi_speed(); set_spi_speed();
pch_early_lpc(); pch_early_lpc();