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sb/intel/lynxpoint: Use common early SPI code 

Change-Id: I6c6fbed077d2f169736aee77af3783c847cf3a06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-06-21 18:04:57 +02:00
parent 8caa53133f
commit 4c7ef81a23
1 changed files with 2 additions and 18 deletions
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20
src/southbridge/intel/lynxpoint/bootblock.c
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@ -2,25 +2,9 @@
#include <arch/bootblock.h>
#include <device/pci_ops.h>
#include <southbridge/intel/common/early_spi.h>
#include "pch.h"
/*
* Enable Prefetching and Caching.
*/
static void enable_spi_prefetch(void)
{
u8 reg8;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, 0xdc);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, 0xdc, reg8);
}
static void map_rcba(void)
{
pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
@ -60,7 +44,7 @@ static void set_spi_speed(void)
void bootblock_early_southbridge_init(void)
{
map_rcba();
enable_spi_prefetch();
enable_spi_prefetching_and_caching();
enable_port80_on_lpc();
set_spi_speed();