soc/intel/broadwell: Use common early SPI code
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -10,18 +10,7 @@
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#include <reg_script.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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/*
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* Enable Prefetching and Caching.
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*/
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static void enable_spi_prefetch(void)
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{
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u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
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}
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#include <southbridge/intel/common/early_spi.h>
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static void map_rcba(void)
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{
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@ -105,7 +94,7 @@ static void pch_early_lpc(void)
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void bootblock_early_southbridge_init(void)
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{
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map_rcba();
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enable_spi_prefetch();
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enable_spi_prefetching_and_caching();
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enable_port80_on_lpc();
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set_spi_speed();
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pch_early_lpc();
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