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mb/google/drallion: Update GPIO table 

Follow latest GPIO table to change gpio.

BUG=b:143728355
BRANCH=N/A
TEST=build pass

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
This commit is contained in:
Eric Lai 2019-11-01 13:36:37 +08:00 committed by Patrick Georgi
parent 3d4f51ef69
commit 5407571168
1 changed files with 4 additions and 5 deletions
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9
src/mainboard/google/drallion/variants/drallion/gpio.c
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@ -39,13 +39,13 @@ static const struct pad_config gpio_table[] = {
/* ESPI_RESET# */ /* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP),
/* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ /* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */
/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
/* ISH_ACC1_INT# */ /* ISH_ACC1_INT# */
/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* ISH_ACC2_INT# */ /* ISH_ACC2_INT# */
/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
/* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
/* ISH_NB_MODE */ /* ISH_NB_MODE */
/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
/* ISH_LID_CL#_NB */ /* ISH_LID_CL#_NB */
@ -63,11 +63,10 @@ static const struct pad_config gpio_table[] = {
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* WLAN_CLKREQ_CPU_N */ /* WLAN_CLKREQ_CPU_N */
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* WWAN_CLKREQ_CPU_N */ /* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE),
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
/* SSD_CKLREQ_CPU_N */ /* SSD_CKLREQ_CPU_N */
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),