- Changes to the pci config routines moving them closer to the non romcc API
The goal is to have the same interface with or without romcc. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
05f26fcb57
commit
540ae01cd3
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@ -53,9 +53,15 @@ static void wrmsr(unsigned long index, msr_t msr)
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(((FN) & 0x07) << 8) | \
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(((FN) & 0x07) << 8) | \
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((WHERE) & 0xFF))
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((WHERE) & 0xFF))
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x7) << 8))
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#define PCI_ID(VENDOR_ID, DEVICE_ID) \
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#define PCI_ID(VENDOR_ID, DEVICE_ID) \
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((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
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((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
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#if 0
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static unsigned char pci_read_config8(unsigned addr)
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static unsigned char pci_read_config8(unsigned addr)
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{
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{
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(0x80000000 | (addr & ~3), 0xCF8);
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@ -104,3 +110,68 @@ static unsigned pci_locate_device(unsigned pci_id, unsigned addr)
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}
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}
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return ~0U;
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return ~0U;
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}
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}
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#else
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typedef unsigned device_t;
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static unsigned char pci_read_config8(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inb(0xCFC + (addr & 3));
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}
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static unsigned short pci_read_config16(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inw(0xCFC + (addr & 2));
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}
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static unsigned int pci_read_config32(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inl(0xCFC);
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}
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static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outb(value, 0xCFC + (addr & 3));
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}
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static void pci_write_config16(device_t dev, unsigned where, unsigned short value)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outw(value, 0xCFC + (addr & 2));
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}
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static void pci_write_config32(device_t dev, unsigned where, unsigned int value)
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{
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unsigned addr;
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addr = dev | where;
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(value, 0xCFC);
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}
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#define PCI_DEV_INVALID (0xffffffffU)
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static device_t pci_locate_device(unsigned pci_id, device_t dev)
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{
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for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
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unsigned int id;
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id = pci_read_config32(dev, 0);
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if (id == pci_id) {
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return dev;
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}
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}
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return PCI_DEV_INVALID;
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}
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#endif
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@ -33,7 +33,7 @@ static int cpu_init_detected(void)
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unsigned long htic;
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unsigned long htic;
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htic = pci_read_config32(PCI_ADDR(0, 0x18, 0, HT_INIT_CONTROL));
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htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
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#if 0
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#if 0
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print_debug("htic: ");
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print_debug("htic: ");
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print_debug_hex32(htic);
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print_debug_hex32(htic);
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@ -59,21 +59,21 @@ static int cpu_init_detected(void)
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static void print_pci_devices(void)
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static void print_pci_devices(void)
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{
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{
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uint32_t addr;
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device_t dev;
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for(addr = PCI_ADDR(0, 0, 0, 0);
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for(dev = PCI_DEV(0, 0, 0);
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addr <= PCI_ADDR(0, 0x1f, 0x7, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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addr += PCI_ADDR(0,0,1,0)) {
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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uint32_t id;
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id = pci_read_config32(addr + PCI_VENDOR_ID);
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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continue;
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}
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}
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print_debug("PCI: 00:");
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print_debug("PCI: 00:");
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print_debug_hex8(addr >> 11);
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print_debug_hex8(dev >> 11);
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print_debug_char('.');
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print_debug_char('.');
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print_debug_hex8((addr >> 8) & 7);
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print_debug_hex8((dev >> 8) & 7);
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print_debug("\r\n");
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print_debug("\r\n");
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}
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}
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}
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}
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@ -111,82 +111,10 @@ static void dump_spd_registers(void)
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}
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}
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static void pnp_write_config(unsigned char port, unsigned char value, unsigned char reg)
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{
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outb(reg, port);
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outb(value, port +1);
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}
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static unsigned char pnp_read_config(unsigned char port, unsigned char reg)
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{
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outb(reg, port);
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return inb(port +1);
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}
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static void pnp_set_logical_device(unsigned char port, int device)
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{
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pnp_write_config(port, device, 0x07);
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}
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static void pnp_set_enable(unsigned char port, int enable)
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{
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pnp_write_config(port, enable?0x1:0x0, 0x30);
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}
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static int pnp_read_enable(unsigned char port)
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{
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return !!pnp_read_config(port, 0x30);
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}
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static void pnp_set_iobase0(unsigned char port, unsigned iobase)
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{
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pnp_write_config(port, (iobase >> 8) & 0xff, 0x60);
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pnp_write_config(port, iobase & 0xff, 0x61);
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}
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static void pnp_set_iobase1(unsigned char port, unsigned iobase)
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{
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pnp_write_config(port, (iobase >> 8) & 0xff, 0x62);
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pnp_write_config(port, iobase & 0xff, 0x63);
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}
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static void pnp_set_irq0(unsigned char port, unsigned irq)
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{
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pnp_write_config(port, irq, 0x70);
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}
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static void pnp_set_irq1(unsigned char port, unsigned irq)
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{
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pnp_write_config(port, irq, 0x72);
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}
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static void pnp_set_drq(unsigned char port, unsigned drq)
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{
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pnp_write_config(port, drq & 0xff, 0x74);
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}
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#define PC87360_FDC 0x00
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#define PC87360_PP 0x01
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#define PC87360_SP2 0x02
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#define PC87360_SP1 0x03
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#define PC87360_SWC 0x04
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#define PC87360_KBCM 0x05
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#define PC87360_KBCK 0x06
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#define PC87360_GPIO 0x07
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#define PC87360_ACB 0x08
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#define PC87360_FSCM 0x09
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#define PC87360_WDT 0x0A
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static void pc87360_enable_serial(void)
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{
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pnp_set_logical_device(SIO_BASE, PC87360_SP1);
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pnp_set_enable(SIO_BASE, 1);
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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static void main(void)
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static void main(void)
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{
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{
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pc87360_enable_serial();
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uart_init();
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uart_init();
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console_init();
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console_init();
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if (boot_cpu() && !cpu_init_detected()) {
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if (boot_cpu() && !cpu_init_detected()) {
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@ -574,6 +574,8 @@ static void setup_coherent_ht_domain(void)
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print_debug("setting up coherent ht domain....\r\n");
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print_debug("setting up coherent ht domain....\r\n");
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max = sizeof(register_values)/sizeof(register_values[0]);
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max = sizeof(register_values)/sizeof(register_values[0]);
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for(i = 0; i < max; i += 3) {
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for(i = 0; i < max; i += 3) {
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device_t dev;
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unsigned where;
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unsigned long reg;
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unsigned long reg;
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#if 0
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#if 0
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print_debug_hex32(register_values[i]);
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print_debug_hex32(register_values[i]);
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@ -581,10 +583,18 @@ static void setup_coherent_ht_domain(void)
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print_debug_hex32(register_values[i+2]);
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print_debug_hex32(register_values[i+2]);
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print_debug("\r\n");
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print_debug("\r\n");
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#endif
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#endif
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dev = register_values[i] & ~0xff;
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where = register_values[i] & 0xff;
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reg = pci_read_config32(dev, where);
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reg &= register_values[i+1];
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reg |= register_values[i+2];
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pci_write_config32(dev, where, reg);
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#if 0
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reg = pci_read_config32(register_values[i]);
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reg = pci_read_config32(register_values[i]);
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reg &= register_values[i+1];
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reg &= register_values[i+1];
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reg |= register_values[i+2] & ~register_values[i+1];
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reg |= register_values[i+2] & ~register_values[i+1];
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pci_write_config32(register_values[i], reg);
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pci_write_config32(register_values[i], reg);
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#endif
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}
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}
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print_debug("done.\r\n");
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print_debug("done.\r\n");
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}
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}
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@ -12,38 +12,38 @@ static void enumerate_ht_chain(void)
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uint8_t hdr_type, pos;
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uint8_t hdr_type, pos;
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last_unitid = next_unitid;
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last_unitid = next_unitid;
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id = pci_read_config32(PCI_ADDR(0,0,0,PCI_VENDOR_ID));
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id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
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/* If the chain is enumerated quit */
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/* If the chain is enumerated quit */
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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(((id >> 16) & 0xffff) == 0x0000)) {
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break;
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break;
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}
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}
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hdr_type = pci_read_config8(PCI_ADDR(0,0,0,PCI_HEADER_TYPE));
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hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
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pos = 0;
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pos = 0;
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hdr_type &= 0x7f;
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hdr_type &= 0x7f;
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if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
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if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
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(hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
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(hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
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pos = pci_read_config8(PCI_ADDR(0,0,0, PCI_CAPABILITY_LIST));
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pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
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}
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}
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while(pos != 0) {
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while(pos != 0) {
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uint8_t cap;
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uint8_t cap;
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cap = pci_read_config8(PCI_ADDR(0,0,0, pos + PCI_CAP_LIST_ID));
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cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
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if (cap == PCI_CAP_ID_HT) {
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if (cap == PCI_CAP_ID_HT) {
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uint16_t flags;
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uint16_t flags;
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flags = pci_read_config16(PCI_ADDR(0,0,0, pos + PCI_CAP_FLAGS));
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flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
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if ((flags >> 13) == 0) {
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if ((flags >> 13) == 0) {
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unsigned count;
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unsigned count;
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flags &= ~0x1f;
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flags &= ~0x1f;
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flags |= next_unitid & 0x1f;
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flags |= next_unitid & 0x1f;
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count = (flags >> 5) & 0x1f;
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count = (flags >> 5) & 0x1f;
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pci_write_config16(PCI_ADDR(0, 0, 0, pos + PCI_CAP_FLAGS), flags);
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pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
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next_unitid += count;
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next_unitid += count;
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break;
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break;
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}
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}
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}
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}
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pos = pci_read_config8(PCI_ADDR(0, 0, 0, pos + PCI_CAP_LIST_NEXT));
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pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
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}
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}
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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}
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}
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@ -692,6 +692,8 @@ static void sdram_set_registers(void)
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print_debug("setting up CPU0 northbridge registers\r\n");
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print_debug("setting up CPU0 northbridge registers\r\n");
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max = sizeof(register_values)/sizeof(register_values[0]);
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max = sizeof(register_values)/sizeof(register_values[0]);
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for(i = 0; i < max; i += 3) {
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for(i = 0; i < max; i += 3) {
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device_t dev;
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unsigned where;
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unsigned long reg;
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unsigned long reg;
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#if 0
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#if 0
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print_debug_hex32(register_values[i]);
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print_debug_hex32(register_values[i]);
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@ -699,10 +701,19 @@ static void sdram_set_registers(void)
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print_debug_hex32(register_values[i+2]);
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print_debug_hex32(register_values[i+2]);
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print_debug("\r\n");
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print_debug("\r\n");
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#endif
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#endif
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dev = register_values[i] & ~0xff;
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where = register_values[i] & 0xff;
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reg = pci_read_config32(dev, where);
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reg &= register_values[i+1];
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reg |= register_values[i+2];
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pci_write_config32(dev, where, reg);
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#if 0
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reg = pci_read_config32(register_values[i]);
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reg = pci_read_config32(register_values[i]);
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reg &= register_values[i+1];
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reg &= register_values[i+1];
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reg |= register_values[i+2];
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reg |= register_values[i+2];
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pci_write_config32(register_values[i], reg);
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pci_write_config32(register_values[i], reg);
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#endif
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}
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}
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print_debug("done.\r\n");
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print_debug("done.\r\n");
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}
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}
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@ -727,10 +738,10 @@ static void sdram_set_registers(void)
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static void sdram_set_spd_registers(void)
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static void sdram_set_spd_registers(void)
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{
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{
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unsigned long dcl;
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unsigned long dcl;
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dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
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dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
|
||||||
/* Until I know what is going on disable ECC support */
|
/* Until I know what is going on disable ECC support */
|
||||||
dcl &= ~DCL_DimmEcEn;
|
dcl &= ~DCL_DimmEcEn;
|
||||||
pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl);
|
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
|
||||||
}
|
}
|
||||||
|
|
||||||
#define TIMEOUT_LOOPS 300000
|
#define TIMEOUT_LOOPS 300000
|
||||||
|
@ -739,23 +750,23 @@ static void sdram_enable(void)
|
||||||
unsigned long dcl;
|
unsigned long dcl;
|
||||||
|
|
||||||
/* Toggle DisDqsHys to get it working */
|
/* Toggle DisDqsHys to get it working */
|
||||||
dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
|
dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
|
||||||
print_debug("dcl: ");
|
print_debug("dcl: ");
|
||||||
print_debug_hex32(dcl);
|
print_debug_hex32(dcl);
|
||||||
print_debug("\r\n");
|
print_debug("\r\n");
|
||||||
dcl |= DCL_DisDqsHys;
|
dcl |= DCL_DisDqsHys;
|
||||||
pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl);
|
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
|
||||||
dcl &= ~DCL_DisDqsHys;
|
dcl &= ~DCL_DisDqsHys;
|
||||||
dcl &= ~DCL_DLL_Disable;
|
dcl &= ~DCL_DLL_Disable;
|
||||||
dcl &= ~DCL_D_DRV;
|
dcl &= ~DCL_D_DRV;
|
||||||
dcl &= ~DCL_QFC_EN;
|
dcl &= ~DCL_QFC_EN;
|
||||||
dcl |= DCL_DramInit;
|
dcl |= DCL_DramInit;
|
||||||
pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl);
|
pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
|
||||||
|
|
||||||
print_debug("Initializing memory: ");
|
print_debug("Initializing memory: ");
|
||||||
int loops = 0;
|
int loops = 0;
|
||||||
do {
|
do {
|
||||||
dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
|
dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
|
||||||
loops += 1;
|
loops += 1;
|
||||||
if ((loops & 1023) == 0) {
|
if ((loops & 1023) == 0) {
|
||||||
print_debug(".");
|
print_debug(".");
|
||||||
|
@ -771,7 +782,7 @@ static void sdram_enable(void)
|
||||||
print_debug("Clearing memory: ");
|
print_debug("Clearing memory: ");
|
||||||
loops = 0;
|
loops = 0;
|
||||||
do {
|
do {
|
||||||
dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
|
dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
|
||||||
loops += 1;
|
loops += 1;
|
||||||
if ((loops & 1023) == 0) {
|
if ((loops & 1023) == 0) {
|
||||||
print_debug(" ");
|
print_debug(" ");
|
||||||
|
|
|
@ -11,16 +11,16 @@
|
||||||
|
|
||||||
static void enable_smbus(void)
|
static void enable_smbus(void)
|
||||||
{
|
{
|
||||||
uint32_t addr;
|
device_t dev;
|
||||||
addr = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
|
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
|
||||||
if (addr == ~0U) {
|
if (dev == PCI_DEV_INVALID) {
|
||||||
die("SMBUS controller not found\r\n");
|
die("SMBUS controller not found\r\n");
|
||||||
}
|
}
|
||||||
uint8_t enable;
|
uint8_t enable;
|
||||||
print_debug("SMBus controller enabled\r\n");
|
print_debug("SMBus controller enabled\r\n");
|
||||||
pci_write_config32(addr + 0x58, SMBUS_IO_BASE | 1);
|
pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
|
||||||
enable = pci_read_config8(addr + 0x41);
|
enable = pci_read_config8(dev, 0x41);
|
||||||
pci_write_config8(addr + 0x41, enable | (1 << 7));
|
pci_write_config8(dev, 0x41, enable | (1 << 7));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -2,17 +2,14 @@
|
||||||
static void amd8111_enable_rom(void)
|
static void amd8111_enable_rom(void)
|
||||||
{
|
{
|
||||||
unsigned char byte;
|
unsigned char byte;
|
||||||
uint32_t addr;
|
device_t addr;
|
||||||
|
|
||||||
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
|
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
|
||||||
/* Locate the amd8111 */
|
/* Locate the amd8111 */
|
||||||
addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
|
addr = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
|
||||||
|
|
||||||
/* Refine the address to point at the rom enable byte */
|
|
||||||
addr += 0x43;
|
|
||||||
|
|
||||||
/* Set the 4MB enable bit bit */
|
/* Set the 4MB enable bit bit */
|
||||||
byte = pci_read_config8(addr);
|
byte = pci_read_config8(addr, 0x43);
|
||||||
byte |= 0x80;
|
byte |= 0x80;
|
||||||
pci_write_config8(addr, byte);
|
pci_write_config8(addr, 0x43, byte);
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue