soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL was incorrectly updated to use << (ShiftLeft) instead of >> (ShiftRight). This change fixes the error in GPCL by updating it to use >> (ShiftRight). TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for hatch. Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
eb72487784
commit
5434deaf2a
|
@ -229,7 +229,7 @@ Method (GPCB, 0, Serialized)
|
|||
/* Get PCIe Length */
|
||||
Method (GPCL, 0, Serialized)
|
||||
{
|
||||
Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ
|
||||
Local0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue