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soc/intel/apollolake: Make use of is_devfn_enabled() function 

1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.

TEST=Able to build and boot without any regression seen on Reef.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2021-06-09 03:54:58 +05:30
parent 09a6d633ae
commit 54a3417254
3 changed files with 5 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/apollolake/acpi.c
View File

@ -143,7 +143,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
static unsigned long soc_fill_dmar(unsigned long current)
{
struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@ -151,7 +150,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
unsigned long tmp;
/* IGD has to be enabled, GFXVTBAR set and enabled. */
const bool emit_igd = is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten;
const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
/* First, add DRHD entries */
if (emit_igd) {

7
src/soc/intel/apollolake/chip.c
View File

@ -533,7 +533,6 @@ static void glk_fsp_silicon_init_params_cb(
{
#if CONFIG(SOC_INTEL_GEMINILAKE)
uint8_t port;
struct device *dev;
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
if (!cfg->usb2eye[port].Usb20OverrideEn)
@ -549,8 +548,7 @@ static void glk_fsp_silicon_init_params_cb(
cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
}
dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM);
silconfig->Gmm = is_dev_enabled(dev);
silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM);
/* On Geminilake, we need to override the default FSP PCIe de-emphasis
* settings using the device tree settings. This is because PCIe
@ -693,8 +691,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Set VTD feature according to devicetree */
silconfig->VtdEnable = cfg->enable_vtd;
dev = pcidev_path_on_root(SA_DEVFN_IGD);
silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
silconfig->PavpEnable = CONFIG(PAVP);

6
src/soc/intel/apollolake/romstage.c
View File

@ -256,12 +256,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
static void parse_devicetree_setting(FSPM_UPD *m_upd)
{
DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
#if CONFIG(SOC_INTEL_GEMINILAKE)
m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev);
m_upd->FspmConfig.TraceHubEn = is_devfn_enabled(PCH_DEVFN_NPK);
#else
m_upd->FspmConfig.NpkEn = is_dev_enabled(dev);
m_upd->FspmConfig.NpkEn = is_devfn_enabled(PCH_DEVFN_NPK);
#endif
}