more chip stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -1,5 +1,18 @@
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#ifndef PNP_INDEX_REG
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#define PNP_INDEX_REG 0x15C
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#endif
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#ifndef PNP_DATA_REG
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#define PNP_DATA_REG 0x15D
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#endif
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#ifndef SIO_COM1
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#define SIO_COM1_BASE 0x3F8
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#endif
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#ifndef SIO_COM2
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#define SIO_COM2_BASE 0x2F8
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#endif
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struct superio_NSC_pc97307_config {
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typedef struct com_ports com1;
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typedef struct lpt_ports lpt;
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struct com_ports com1;
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struct lpt_ports lpt;
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int port;
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};
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@ -3,19 +3,7 @@
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#include <arch/io.h>
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#include <device/chip.h>
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#ifndef PNP_INDEX_REG
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#define PNP_INDEX_REG 0x15C
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#endif
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#ifndef PNP_DATA_REG
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#define PNP_DATA_REG 0x15D
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#endif
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#ifndef SIO_COM1
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#define SIO_COM1_BASE 0x3F8
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#endif
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#ifndef SIO_COM2
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#define SIO_COM2_BASE 0x2F8
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#endif
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#include "chip.h"
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void pnp_output(char address, char data)
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{
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@ -25,22 +13,25 @@ void pnp_output(char address, char data)
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void sio_enable(struct chip *chip, enum chip_pass pass)
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{
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struct superio_NSC_pc97307_config *conf = (struct superio_NSC_pc97307_config *)chip->chip_info;
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switch (pass) {
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case CHIP_PRE_CONSOLE:
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/* Enable Super IO Chip */
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pnp_output(0x07, 6); /* LD 6 = UART1 */
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pnp_output(0x30, 0); /* Dectivate */
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pnp_output(0x60, chip->control->defaultport >> 8); /* IO Base */
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pnp_output(0x61, chip->control->defaultport & 0xFF); /* IO Base */
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pnp_output(0x60, conf->port >> 8); /* IO Base */
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pnp_output(0x61, conf->port & 0xFF); /* IO Base */
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pnp_output(0x30, 1); /* Activate */
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break;
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default:
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/* nothing yet */
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break;
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}
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}
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struct superio_control superio_NSC_pc97307_control = {
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enable: sio_enable,
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defaultport: SIO_COM1_BASE,
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name: "NSC 87307"
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struct chip_control superio_NSC_pc97307_control = {
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enable: sio_enable,
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name: "NSC 87307"
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};
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