sb/{ICH7,NM10,PCH}: Use common watchdog_off function

Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian

src/southbridge/intel/bd82x6x/Kconfig

@@ -44,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 	select SOUTHBRIDGE_INTEL_COMMON_SMM
 	select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 config EHCI_BAR
 	hex

src/southbridge/intel/bd82x6x/Makefile.inc

@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 ramstage-y += me_status.c
-ramstage-y += watchdog.c
 
 ramstage-$(CONFIG_ELOG) += elog.c
 

src/southbridge/intel/common/Kconfig

@@ -65,6 +65,10 @@ config INTEL_CHIPSET_LOCKDOWN
 	  and S3 resume (always done by coreboot). Select this to let coreboot
 	  to do this on normal boot path.
 
+config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
+	bool
+	depends on SOUTHBRIDGE_INTEL_COMMON
+
 if SOUTHBRIDGE_INTEL_COMMON_FINALIZE
 
 choice

src/southbridge/intel/common/Makefile.inc

@@ -27,6 +27,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
 
 romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c
 
+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
 
 verstage-y += pmbase.c

src/southbridge/intel/common/tco.h

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2019 Elyes Haouas <ehaouas@noos.fr>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H
+#define SOUTHBRIDGE_INTEL_COMMON_TCO_H
+
+#define PMBASE_TCO_OFFSET	0x60
+#define TCO1_STS		0x04
+#define  TCO1_TIMEOUT		(1 << 3)
+#define TCO2_STS		0x06
+#define  SECOND_TO_STS		(1 << 1)
+#define TCO1_CNT		0x08
+#define  TCO_TMR_HLT		(1 << 11)
+
+#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */

src/southbridge/intel/common/watchdog.c

@@ -16,17 +16,16 @@
  */
 
 #include <console/console.h>
-#include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <southbridge/intel/common/pmbase.h>
-#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/common/tco.h>
-
 #include <watchdog.h>
 
 /*
- *  Disable PCH watchdog timer
+ *  Disable ICH-NM10-PCH watchdog timer
  */
 void watchdog_off(void)
 {
@@ -36,21 +35,25 @@ void watchdog_off(void)
 	/* Get LPC device. */
 	dev = pcidev_on_root(0x1f, 0);
 
-	/* Disable interrupt. */
 	value = pci_read_config16(dev, PCI_COMMAND);
+
+	if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) {
+		/* Enable I/O space. */
+		value |= PCI_COMMAND_IO;
+	} else {
+		/* Disable interrupt. */
 		value |= PCI_COMMAND_INT_DISABLE;
+	}
 	pci_write_config16(dev, PCI_COMMAND, value);
 
 	/* Disable the watchdog timer. */
-	value = read_pmbase16(TCO1_CNT);
+	value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
 	value |= TCO_TMR_HLT;
-	write_pmbase16(TCO1_CNT, value);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
 
 	/* Clear TCO timeout status. */
-	write_pmbase16(TCO1_STS, TCO1_TIMEOUT);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
-	write_pmbase16(TCO2_STS, SECOND_TO_STS);
+	write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
 
-	/* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */
+	printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
-
-	printk(BIOS_DEBUG, "PCH: watchdog disabled\n");
 }

src/southbridge/intel/fsp_rangeley/Kconfig

@@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 config EHCI_BAR
 	hex

src/southbridge/intel/fsp_rangeley/Makefile.inc

@@ -19,7 +19,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
 ramstage-y += soc.c
 ramstage-y += lpc.c
 ramstage-y += sata.c
-ramstage-y += watchdog.c
 ramstage-y += spi.c
 ramstage-y += smbus.c
 ramstage-y += acpi.c

src/southbridge/intel/fsp_rangeley/watchdog.c

@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <watchdog.h>
-#include "soc.h"
-
-void watchdog_off(void)
-{
-	struct device *dev;
-	u32 value, abase;
-
-	/* Turn off the watchdog. */
-	dev = pcidev_on_root(0x1f, 0);
-
-	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= 1;
-	pci_write_config16(dev, 0x04, value);
-
-	/* Get TCO base. */
-	abase = (pci_read_config32(dev, ABASE) & ~0xf);
-
-	/* Disable the watchdog timer. */
-	value = inw(abase + 0x68);
-	value |= 1 << 11;
-	outw(value, abase + 0x68);
-
-	/* Clear TCO timeout status. */
-	outw(0x0008, abase + 0x64);
-	outw(0x0002, abase + 0x66);
-
-	printk(BIOS_DEBUG, "TCO Watchdog disabled\n");
-}

src/southbridge/intel/i82801gx/Kconfig

@@ -30,6 +30,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select INTEL_HAS_TOP_SWAP
 	select SOUTHBRIDGE_INTEL_COMMON_SMM
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 if SOUTHBRIDGE_INTEL_I82801GX
 

src/southbridge/intel/i82801gx/Makefile.inc

@@ -30,8 +30,6 @@ ramstage-y += usb_ehci.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ramstage-y += watchdog.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c

src/southbridge/intel/i82801gx/watchdog.c

@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <watchdog.h>
-
-void watchdog_off(void)
-{
-	struct device *dev;
-	unsigned long value, base;
-
-	/* Turn off the ICH7 watchdog. */
-	dev = pcidev_on_root(0x1f, 0);
-
-	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Get TCO base. */
-	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-
-	/* Disable the watchdog timer. */
-	value = inw(base + 0x08);
-	value |= 1 << 11;
-	outw(value, base + 0x08);
-
-	/* Clear TCO timeout status. */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
-
-	printk(BIOS_DEBUG, "ICH7 watchdog disabled\n");
-}

src/southbridge/intel/i82801ix/Kconfig

@@ -29,6 +29,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
 	select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 if SOUTHBRIDGE_INTEL_I82801IX
 

src/southbridge/intel/i82801ix/Makefile.inc

@@ -29,8 +29,6 @@ ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ramstage-y += ../i82801gx/watchdog.c
-
 ifneq ($(CONFIG_SMM_TSEG),y)
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S

src/southbridge/intel/i82801jx/Kconfig

@@ -33,6 +33,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select HAVE_POWER_STATE_AFTER_FAILURE
 	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 if SOUTHBRIDGE_INTEL_I82801JX
 

src/southbridge/intel/i82801jx/Makefile.inc

@@ -29,8 +29,6 @@ ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ramstage-y += ../i82801gx/watchdog.c
-
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c

src/southbridge/intel/ibexpeak/Kconfig

@@ -40,6 +40,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 	select HAVE_POWER_STATE_AFTER_FAILURE
 	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 config EHCI_BAR
 	hex

src/southbridge/intel/ibexpeak/Makefile.inc

@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
 ramstage-y += ../bd82x6x/me_status.c
-ramstage-y += ../bd82x6x/watchdog.c
 
 ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
 ramstage-y += madt.c

src/southbridge/intel/lynxpoint/Kconfig

@@ -42,6 +42,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select COMMON_FADT
 	select HAVE_POWER_STATE_AFTER_FAILURE
 	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
 
 config INTEL_LYNXPOINT_LP
 	bool

src/southbridge/intel/lynxpoint/Makefile.inc

@@ -37,7 +37,6 @@ endif
 
 ramstage-y += rcba.c
 ramstage-y += me_status.c
-ramstage-y += watchdog.c
 ramstage-y += acpi.c
 
 ramstage-$(CONFIG_ELOG) += elog.c

src/southbridge/intel/lynxpoint/watchdog.c

@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <watchdog.h>
-
-  //
-  //  Disable PCH Watchdog timer at SB_RCBA+0x3410
-  //
-  //  Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
-  //
-void watchdog_off(void)
-{
-	struct device *dev;
-	unsigned long value, base;
-
-	/* Turn off the ICH7 watchdog. */
-	dev = pcidev_on_root(0x1f, 0);
-
-	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Get TCO base. */
-	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-
-	/* Disable the watchdog timer. */
-	value = inw(base + 0x08);
-	value |= 1 << 11;
-	outw(value, base + 0x08);
-
-	/* Clear TCO timeout status. */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
-
-	printk(BIOS_DEBUG, "PCH watchdog disabled\n");
-}