GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Derive lvds_dual_channel from EDID timings. 

Based on the info by Felix Held.

Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Vladimir Serbinenko 2015-10-10 23:58:08 +02:00
parent 68c70994e5
commit 551cff08d5
22 changed files with 51 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/drivers/intel/gma/i915.h
View File

@ -288,7 +288,6 @@ u32 gtt_read(u32 reg);
struct i915_gpu_controller_info
{
int use_spread_spectrum_clock;
int lvds_dual_channel;
int link_frequency_270_mhz;
int lvds_num_lanes;
u32 backlight;

1
src/include/edid.h
View File

@ -33,6 +33,7 @@ enum edid_modes {
struct edid_mode {
const char *name;
unsigned int pixel_clock;
int lvds_dual_channel;
unsigned int refresh;
unsigned int ha;
unsigned int hbl;

15
src/lib/edid.c
View File

@ -446,6 +446,21 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension,
if (! c->did_detailed_timing){
/* Edid contains pixel clock in terms of 10KHz */
out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10;
/*
LVDS supports following pixel clocks
25000...112000 kHz: single channel
80000...224000 kHz: dual channel
There is some overlap in theoretically supported
pixel clock between single-channel and dual-channel.
In practice with current panels all panels
<= 75200 kHz: single channel
>= 97750 kHz: dual channel
We have no samples between those values, so put a
threshold at 95000 kHz. If we get anything over
95000 kHz with single channel, we can make this
more sofisticated but it's currently not needed.
*/
out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000);
extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4));
extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8));
out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4));

1
src/mainboard/apple/macbook21/devicetree.cb
View File

@ -26,7 +26,6 @@ chip northbridge/intel/i945
register "gpu_hotplug" = "0x00000220"
register "gpu_lvds_use_spread_spectrum_clock" = "1"
register "gpu_lvds_is_dual_channel" = "0"
register "gpu_backlight" = "0x1290128"
device cpu_cluster 0 on

1
src/mainboard/lenovo/t400/devicetree.cb
View File

@ -4,7 +4,6 @@ chip northbridge/intel/gm45
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "0"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"

1
src/mainboard/lenovo/t420s/devicetree.cb
View File

@ -13,7 +13,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "1"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"

1
src/mainboard/lenovo/t430s/devicetree.cb
View File

@ -13,7 +13,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "1"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155"

1
src/mainboard/lenovo/t520/devicetree.cb
View File

@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "1"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"

1
src/mainboard/lenovo/t530/devicetree.cb
View File

@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "1"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155"

1
src/mainboard/lenovo/x200/devicetree.cb
View File

@ -4,7 +4,6 @@ chip northbridge/intel/gm45
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "0"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"

1
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -38,7 +38,6 @@ chip northbridge/intel/nehalem
register "gpu_cpu_backlight" = "0x58d"
register "gpu_pch_backlight" = "0x061a061a"
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "0"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"

1
src/mainboard/lenovo/x220/devicetree.cb
View File

@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "0"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"

1
src/mainboard/lenovo/x230/devicetree.cb
View File

@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "0"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155"

1
src/mainboard/lenovo/x60/devicetree.cb
View File

@ -26,7 +26,6 @@ chip northbridge/intel/i945
register "gpu_hotplug" = "0x00000220"
register "gpu_lvds_use_spread_spectrum_clock" = "1"
register "gpu_lvds_is_dual_channel" = "0"
register "gpu_backlight" = "0x1290128"
device cpu_cluster 0 on

1
src/mainboard/packardbell/ms2290/devicetree.cb
View File

@ -38,7 +38,6 @@ chip northbridge/intel/nehalem
register "gpu_cpu_backlight" = "0x58d"
register "gpu_pch_backlight" = "0x061a061a"
register "gfx.use_spread_spectrum_clock" = "0"
register "gfx.lvds_dual_channel" = "1"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"

14
src/northbridge/intel/gm45/gma.c
View File

@ -174,7 +174,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
hfront_porch = mode->hso;
vfront_porch = mode->vso;
target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_sr_write(1, 1);
@ -259,7 +259,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG,
info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -276,7 +276,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
mdelay(1);
@ -287,7 +287,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
| ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
@ -295,7 +295,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
mdelay(1);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
@ -306,7 +306,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
@ -397,7 +397,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);

1
src/northbridge/intel/i945/chip.h
View File

@ -4,6 +4,5 @@ struct northbridge_intel_i945_config {
u32 gpu_hotplug;
u32 gpu_backlight;
int gpu_lvds_use_spread_spectrum_clock;
int gpu_lvds_is_dual_channel;
struct i915_gpu_controller_info gfx;
};

10
src/northbridge/intel/i945/gma.c
View File

@ -162,7 +162,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
target_frequency = conf->gpu_lvds_is_dual_channel ? mode->pixel_clock
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
/* Find suitable divisors. */
@ -212,7 +212,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock
? "Spread spectrum clock\n"
: "DREF clock\n"));
printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel
printk(BIOS_DEBUG, (mode->lvds_dual_channel
? "Dual channel\n"
: "Single channel\n"));
printk(BIOS_DEBUG, "Polarities %d, %d\n",
@ -251,7 +251,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
write32(pmmio + DPLL(1),
DPLL_VGA_MODE_DIS |
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (conf->gpu_lvds_use_spread_spectrum_clock
? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
@ -262,7 +262,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
write32(pmmio + DPLL(1),
DPLL_VGA_MODE_DIS |
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
| (pixel_p1 << 16)
@ -318,7 +318,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
write32(pmmio + PIPECONF(1), PIPECONF_ENABLE);
write32(pmmio + LVDS, LVDS_ON
| (hpolarity << 20) | (vpolarity << 21)
| (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_CLOCK_A_POWERUP_ALL
| LVDS_PIPE(1));

14
src/northbridge/intel/nehalem/gma.c
View File

@ -722,7 +722,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
hfront_porch = mode->hso;
vfront_porch = mode->vso;
target_frequency = info->gfx.lvds_dual_channel ? mode->pixel_clock
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
vga_textmode_init();
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
@ -807,7 +807,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG,
info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -824,7 +824,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
@ -839,7 +839,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
| ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
@ -847,7 +847,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
mdelay(1);
write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
@ -858,7 +858,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
@ -955,7 +955,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);

17
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
View File

@ -231,8 +231,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 candp1, candn;
u32 best_delta = 0xffffffff;
u32 target_frequency = info->lvds_dual_channel ? edid.mode.pixel_clock
: (2 * edid.mode.pixel_clock);
u32 target_frequency = (
edid.mode.lvds_dual_channel ? edid.mode.pixel_clock
: (2 * edid.mode.pixel_clock));
u32 pixel_p1 = 1;
u32 pixel_n = 1;
u32 pixel_m1 = 1;
@ -327,7 +328,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG,
info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
edid.mode.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -344,7 +345,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
@ -359,7 +360,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
| ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (edid.mode.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
@ -371,7 +372,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
mdelay(1);
write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (edid.mode.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
@ -382,7 +383,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
@ -482,7 +483,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);

14
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
View File

@ -205,7 +205,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
hfront_porch = mode->hso;
vfront_porch = mode->vso;
target_frequency = info->lvds_dual_channel ? mode->pixel_clock
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
@ -291,7 +291,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG,
info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -308,7 +308,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
@ -324,7 +324,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_DPLL_SEL, 8);
write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
@ -332,7 +332,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
mdelay(1);
write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
@ -343,7 +343,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);
@ -441,7 +441,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
| (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED);

1
util/autoport/sandybridge.go
View File

@ -54,7 +54,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
"gfx.lvds_dual_channel": FormatBool(dualChannel),
"gfx.lvds_num_lanes": FormatInt32(num_lanes),
"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
/* FIXME:XX hardcoded. */