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soc/intel/alderlake: Avoid redundant chipset programming in romstage 

This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.

This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.

TEST=Able to build and boot Google/Marasov successfully.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2023-01-16 13:24:47 +05:30 committed by Felix Held
parent b486fe95bf
commit 55812d6430
1 changed files with 14 additions and 14 deletions
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28
src/soc/intel/alderlake/romstage/romstage.c
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@ -128,15 +128,26 @@ static void save_dimm_info(void)
void mainboard_romstage_entry(void)
{
bool s3wake;
struct chipset_power_state *ps = pmc_get_power_state();
bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
/* Initialize HECI interface */
cse_init(HECI1_BASE_ADDRESS);
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
dbg_feature_cntrl_init();
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
}
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* Program SMBus base address and enable it */
smbus_common_init();
/* Initialize HECI interface */
cse_init(HECI1_BASE_ADDRESS);
/*
* Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`.
*
@ -145,17 +156,6 @@ void mainboard_romstage_entry(void)
if (!CONFIG(INTEL_TXT))
disable_intel_txt();
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
dbg_feature_cntrl_init();
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
timestamp_add_now(TS_CSE_FW_SYNC_END);
}
/* Update coreboot timestamp table with CSE timestamps */
if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
cse_get_telemetry_data();