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mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4 

This change disables unused PCIE RP8 and CLKSRC4. Without this change
storo cannot enter into s0ix properly.

BUG=b:219376808
TEST=Built and verified in storo

Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
This commit is contained in:
Zanxi Chen 2022-09-23 09:59:46 +08:00 committed by Karthik Ramasubramanian
parent 164c5eda27
commit 55d47bd1bf
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/dedede/variants/storo/overridetree.cb
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@ -7,6 +7,10 @@ fw_config
end end
chip soc/intel/jasperlake chip soc/intel/jasperlake
# Disable PCIe Root Port 8 (index 7)
register "PcieRpEnable[7]" = "0"
# Disable PCIe Clock Source 4 (index 3)
register "PcieClkSrcUsage[3]" = "0xff"
# USB Port Configuration # USB Port Configuration
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera