soc/amd/common/block/cpu: Add support for cbfs_cache region
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -24,6 +24,11 @@ config MEMLAYOUT_LD_FILE
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string
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string
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default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
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default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
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config CBFS_CACHE_SIZE
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hex
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help
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The size of the cbfs_cache region.
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config PAYLOAD_PRELOAD_CACHE_SIZE
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config PAYLOAD_PRELOAD_CACHE_SIZE
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hex
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hex
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default 0x30000
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default 0x30000
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@ -25,6 +25,10 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE;
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* | |
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* | |
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* reserved_dram_end +--------------------------------+
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* reserved_dram_end +--------------------------------+
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* | |
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* | |
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* | cbfs_cache (if reqd) |
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* | (CBFS_CACHE_SIZE) |
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* +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE
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* | |
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* | verstage (if reqd) |
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* | verstage (if reqd) |
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* | (VERSTAGE_SIZE) |
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* | (VERSTAGE_SIZE) |
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* +--------------------------------+ VERSTAGE_ADDR
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* +--------------------------------+ VERSTAGE_ADDR
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@ -95,6 +99,11 @@ SECTIONS
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VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
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VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
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#endif
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#endif
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#if CONFIG_CBFS_CACHE_SIZE > 0
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. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
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CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE)
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#endif
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EARLY_RESERVED_DRAM_END(.)
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EARLY_RESERVED_DRAM_END(.)
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#if CONFIG(PAYLOAD_PRELOAD)
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#if CONFIG(PAYLOAD_PRELOAD)
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