psp_verstage: convert relative address in EFS2
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -36,10 +36,10 @@
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#define APU_EMMC_BASE 0xfedd5000
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#define APU_EMMC_CONFIG_BASE 0xfedd5800
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#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
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#endif /* ENV_X86 */
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#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
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/* I/O Ranges */
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#define ACPI_IO_BASE 0x0400
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#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00)
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@ -29,6 +29,8 @@ struct second_gen_efs { /* todo: expand for Server products */
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uint32_t reserved:31;
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} __attribute__((packed));
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#define EFS_SECOND_GEN 0
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/* Copied from coreboot/util/amdfwtool.h */
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struct embedded_firmware {
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uint32_t signature; /* 0x55aa55aa */
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@ -10,6 +10,7 @@
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#include <console/console.h>
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#include <fmap.h>
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#include <pc80/mc146818rtc.h>
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#include <soc/iomap.h>
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#include <soc/psp_transfer.h>
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#include <security/vboot/vbnv.h>
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#include <security/vboot/misc.h>
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@ -121,6 +122,12 @@ static uint32_t update_boot_region(struct vb2_context *ctx)
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return POSTCODE_BDT1_COOKIE_MISMATCH_ERROR;
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}
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/* EFS2 uses relative address and PSP isn't happy with that */
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if (ef_table->efs_gen.gen == EFS_SECOND_GEN) {
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psp_dir_addr = FLASH_BASE_ADDR + (psp_dir_addr & SPI_ADDR_MASK);
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bios_dir_addr = FLASH_BASE_ADDR + (bios_dir_addr & SPI_ADDR_MASK);
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}
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if (update_psp_bios_dir(&psp_dir_addr, &bios_dir_addr)) {
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printk(BIOS_ERR, "Error: Updated BIOS Directory could not be set.\n");
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return POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR;
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@ -61,10 +61,10 @@
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#define APU_EMMC_BASE 0xfedd5000
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#define APU_EMMC_CONFIG_BASE 0xfedd5800
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#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
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#endif /* ENV_X86 */
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#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
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/* I/O Ranges */
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#define ACPI_IO_BASE 0x400
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#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */
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