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soc/amd/common/block/cpu: Add support for cbfs_cache region 

This change adds the cbfs_cache region into the x86 memlayout. The SoC
or mainboard can decide how big the region should be by specifying
CBFS_CACHE_SIZE.

BUG=b:179699789
TEST=Build guybrush and verify cbfs_cache region wasn't added.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2021-07-23 16:43:18 -06:00 committed by Patrick Georgi
parent fab6e44a95
commit 55fea11f2f
2 changed files with 14 additions and 0 deletions
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5
src/soc/amd/common/block/cpu/Kconfig
View File

@ -24,6 +24,11 @@ config MEMLAYOUT_LD_FILE
string
default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
config CBFS_CACHE_SIZE
hex
help
The size of the cbfs_cache region.
config PAYLOAD_PRELOAD_CACHE_SIZE
hex
default 0x30000

9
src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
View File

@ -25,6 +25,10 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE;
* | |
* reserved_dram_end +--------------------------------+
* | |
* | cbfs_cache (if reqd) |
* | (CBFS_CACHE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE
* | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
@ -95,6 +99,11 @@ SECTIONS
VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
#endif
#if CONFIG_CBFS_CACHE_SIZE > 0
. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE)
#endif
EARLY_RESERVED_DRAM_END(.)
#if CONFIG(PAYLOAD_PRELOAD)