src/include: Drop unneeded empty lines
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
7c79d8302b
commit
563fc0889f
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@ -27,5 +27,4 @@ static inline void __flashconsole_tx_byte(u8 data) {}
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static inline void __flashconsole_tx_flush(void) {}
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#endif /* __CONSOLE_FLASH_ENABLE__ */
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#endif /* CONSOLE_FLASH_H */
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@ -52,6 +52,4 @@ struct em100_msg {
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char data[MAX_MSG_LENGTH];
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} __packed;
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#endif /* CONSOLE_SPI_H */
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@ -66,7 +66,6 @@ typedef struct {
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u64 rsi;
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u64 rdi;
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u64 io_mem_addr;
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u32 io_misc_info;
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@ -6,7 +6,6 @@
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#include <types.h>
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#include <cpu/x86/smm.h>
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/* Intel Revision 30101 SMM State-Save Area
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* The following processor architectures use this:
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* - Westmere
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@ -83,7 +82,6 @@ typedef struct {
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u64 rsi;
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u64 rdi;
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u64 io_mem_addr;
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u32 io_misc_info;
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@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_
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bool cpu_has_alternative_smrr(void);
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#define MSR_PRMRR_PHYS_BASE 0x1f4
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#define MSR_PRMRR_PHYS_MASK 0x1f5
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#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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@ -18,7 +18,6 @@
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*/
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#define PMB1_BASE 0x800
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/* Speedstep related MSRs */
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#define MSR_THERM2_CTL 0x19D
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#define MSR_EBC_FREQUENCY_ID 0x2c
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@ -299,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
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return MCA_ERRTYPE_UNKNOWN;
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}
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/* Helper for setting single MSR bits */
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static inline void msr_set_bit(unsigned int reg, unsigned int bit)
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{
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@ -318,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit)
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wrmsr(reg, msr);
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}
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_X86_MSR_H */
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@ -27,7 +27,6 @@
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#define MTRR_DEF_TYPE_EN (1 << 11)
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#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
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#define IA32_SMRR_PHYS_BASE 0x1f2
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#define IA32_SMRR_PHYS_MASK 0x1f3
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#define SMRR_PHYS_MASK_LOCK (1 << 10)
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@ -3,7 +3,6 @@
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#include <console/post_codes.h>
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#if CONFIG(POST_IO)
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#define post_code(value) \
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movb $value, %al; \
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@ -19,7 +19,6 @@
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#include <device/dram/common.h>
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#include <types.h>
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/**
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* Convenience definitions for SPD offsets
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*
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@ -21,7 +21,6 @@
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#define SPD_DDR4_PART_OFF 329
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#define SPD_DDR4_PART_LEN 20
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/*
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* Module type (byte 3, bits 3:0) of SPD
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* This definition is specific to DDR4. DDR2/3 SPDs have a different structure.
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@ -18,7 +18,6 @@
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#define HT_FREQ_2600Mhz 14
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#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */
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static inline bool offset_unit_id(bool is_sb_ht_chain)
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{
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bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
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@ -137,7 +137,6 @@ struct device_path {
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};
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};
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#define DEVICE_PATH_MAX 40
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#define BUS_PATH_MAX (DEVICE_PATH_MAX+10)
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@ -305,7 +305,6 @@
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#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
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#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
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/* CompactPCI Hotswap Register */
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#define PCI_CHSWP_CSR 2 /* Control and Status Register */
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@ -521,7 +520,6 @@
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#define PCI_PWR_CAP 12 /* Capability */
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#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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@ -517,7 +517,6 @@
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#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505
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#define PCI_DEVICE_ID_NS_87410 0xd001
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#define PCI_VENDOR_ID_TSENG 0x100c
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#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202
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#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205
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@ -1664,7 +1663,6 @@
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#define PCI_DEVICE_ID_ATT_L56XMF 0x0440
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#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480
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#define PCI_VENDOR_ID_SPECIALIX 0x11cb
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#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000
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#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000
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@ -7,7 +7,6 @@
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#include <device/mmio.h>
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#include <device/pci_type.h>
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/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
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* prevent some sub-optimal constant folding. */
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extern u8 *const pci_mmconf;
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@ -67,7 +67,6 @@ struct resource *pnp_get_resource(struct device *dev, unsigned int index);
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void pnp_enable_devices(struct device *dev, struct device_operations *ops,
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unsigned int functions, struct pnp_info *info);
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struct pnp_mode_ops {
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void (*enter_conf_mode)(struct device *dev);
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void (*exit_conf_mode)(struct device *dev);
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@ -109,7 +109,6 @@ static inline void *res2mmio(struct resource *res, unsigned long offset,
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const struct device *largest_resource(struct bus *bus, struct resource **result_res,
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unsigned long type_mask, unsigned long type);
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/* Compute and allocate resources. This is the main resource allocator entry point. */
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void allocate_resources(const struct device *root);
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@ -43,8 +43,6 @@ struct fdt_property
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uint32_t size;
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};
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/*
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* Unflattened device tree structures.
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*/
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@ -88,8 +86,6 @@ struct device_tree
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struct device_tree_node *root;
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};
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/*
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* Flattened device tree functions. These generally return the number of bytes
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* which were consumed reading the requested value.
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@ -109,8 +105,6 @@ int fdt_skip_node(const void *blob, uint32_t offset);
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invalidates the unflattened one. */
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struct device_tree *fdt_unflatten(const void *blob);
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/*
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* Unflattened device tree functions.
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*/
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@ -202,7 +202,6 @@ struct elog_event_mem_cache_update {
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#define ELOG_TYPE_MI_HRPC 0xb4
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#define ELOG_TYPE_MI_HR 0xb5
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struct elog_event_extended_event {
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u8 event_type;
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u32 event_complement;
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@ -870,7 +870,6 @@
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#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
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#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */
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#define ABS_MAX 0x3f
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#define ABS_CNT (ABS_MAX+1)
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@ -82,7 +82,6 @@ static inline bool memranges_is_empty(const struct memranges *ranges)
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#define memranges_each_entry(r, ranges) \
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for (r = (ranges)->entries; r != NULL; r = r->next)
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/* Initialize memranges structure providing an optional array of range_entry
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* to use as the free list. Additionally, it accepts an align parameter that
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* represents the required alignment(log 2) of addresses. */
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@ -219,7 +219,6 @@ enum {
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SPEAKER_TOP_BACK_RIGHT = 1 << 17,
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};
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/* Supporting structures. Only SoC/chipset and the library code directly should
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* be manipulating these structures. */
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struct sub_format {
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@ -17,7 +17,6 @@
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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/**********************************************************************
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* register details
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**********************************************************************/
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@ -355,7 +355,6 @@ struct reg_script_bus_entry {
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#define REG_RES_XOR32(bar_, reg_, value_) \
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REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
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#if CONFIG(SOC_INTEL_BAYTRAIL)
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/*
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* IO Sideband Function
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@ -31,7 +31,6 @@ typedef struct { int counter; } atomic_t;
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*/
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#define atomic_set(v, i) (((v)->counter) = (i))
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/**
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* atomic_inc - increment atomic variable
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* @param v: pointer of type atomic_t
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@ -41,7 +40,6 @@ typedef struct { int counter; } atomic_t;
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*/
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#define atomic_inc(v) (((v)->counter)++)
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/**
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* atomic_dec - decrement atomic variable
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* @param v: pointer of type atomic_t
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@ -51,7 +49,6 @@ typedef struct { int counter; } atomic_t;
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*/
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#define atomic_dec(v) (((v)->counter)--)
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#endif /* CONFIG_SMP */
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#endif /* SMP_ATOMIC_H */
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@ -136,7 +136,6 @@
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/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
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#define SPD_tRFC 42
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/* SPD_MEMORY_TYPE values. */
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enum spd_memory_type {
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SPD_MEMORY_TYPE_UNDEFINED = 0x00,
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