soc/amd/picasso: Move sd_emmc_config into emmc_config struct
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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8 changed files with 42 additions and 22 deletions
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@ -112,7 +112,7 @@ static void mainboard_init(void *chip_info)
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struct soc_amd_picasso_config *cfg = config_of_soc();
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if (!CONFIG(PICASSO_LPC_IOMUX))
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cfg->sd_emmc_config = SD_EMMC_EMMC_HS400;
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cfg->emmc_config.timing = SD_EMMC_EMMC_HS400;
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mainboard_program_gpios();
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@ -7,7 +7,9 @@ chip soc/amd/picasso
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register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
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register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
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register "sd_emmc_config" = "SD_EMMC_DISABLE"
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register "emmc_config" = "{
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.timing = SD_EMMC_DISABLE,
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}"
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register "has_usb2_phy_tune_params" = "1"
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@ -40,7 +40,9 @@ chip soc/amd/picasso
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# End : OPN Performance Configuration
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register "sd_emmc_config" = "SD_EMMC_EMMC_HS400"
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register "emmc_config" = "{
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.timing = SD_EMMC_EMMC_HS400,
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}"
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register "xhci0_force_gen1" = "0"
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@ -40,7 +40,9 @@ chip soc/amd/picasso
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# End : OPN Performance Configuration
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register "sd_emmc_config" = "SD_EMMC_EMMC_HS400"
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register "emmc_config" = "{
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.timing = SD_EMMC_EMMC_HS400,
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}"
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register "xhci0_force_gen1" = "0"
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@ -134,10 +134,10 @@ void variant_devtree_update(void)
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* So we keep the speed low here, with the intent that
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* other variants implement these corrections.
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*/
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cfg->sd_emmc_config = SD_EMMC_EMMC_HS200;
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cfg->emmc_config.timing = SD_EMMC_EMMC_HS200;
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}
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} else {
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cfg->sd_emmc_config = SD_EMMC_DISABLE;
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cfg->emmc_config.timing = SD_EMMC_DISABLE;
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}
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update_audio_configuration();
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@ -15,5 +15,5 @@ void variant_devtree_update(void)
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* Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned.
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*/
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if (!(variant_has_emmc() || boot_is_factory_unprovisioned()))
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cfg->sd_emmc_config = SD_EMMC_DISABLE;
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cfg->emmc_config.timing = SD_EMMC_DISABLE;
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}
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@ -126,20 +126,34 @@ struct soc_amd_picasso_config {
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uint32_t telemetry_vddcr_soc_slope;
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uint32_t telemetry_vddcr_soc_offset;
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enum {
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SD_EMMC_DISABLE,
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SD_EMMC_SD_LOW_SPEED,
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SD_EMMC_SD_HIGH_SPEED,
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SD_EMMC_SD_UHS_I_SDR_50,
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SD_EMMC_SD_UHS_I_DDR_50,
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SD_EMMC_SD_UHS_I_SDR_104,
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SD_EMMC_EMMC_SDR_26,
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SD_EMMC_EMMC_SDR_52,
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SD_EMMC_EMMC_DDR_52,
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SD_EMMC_EMMC_HS200,
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SD_EMMC_EMMC_HS400,
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SD_EMMC_EMMC_HS300,
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} sd_emmc_config;
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struct {
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/*
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* SDHCI doesn't directly support eMMC. There is an implicit mapping between
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* eMMC timing modes and SDHCI UHS-I timing modes defined in the linux
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* kernel.
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*
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* HS -> UHS_SDR12 (0x00)
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* DDR52 -> UHS_DDR50 (0x04)
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* HS200 -> UHS_SDR104 (0x03)
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* HS400 -> NONE (0x05)
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*
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* The kernel driver uses a heuristic to determine if HS400 is supported.
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*/
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enum {
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SD_EMMC_DISABLE,
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SD_EMMC_SD_LOW_SPEED,
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SD_EMMC_SD_HIGH_SPEED,
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SD_EMMC_SD_UHS_I_SDR_50,
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SD_EMMC_SD_UHS_I_DDR_50,
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SD_EMMC_SD_UHS_I_SDR_104,
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SD_EMMC_EMMC_SDR_26,
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SD_EMMC_EMMC_SDR_52,
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SD_EMMC_EMMC_DDR_52,
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SD_EMMC_EMMC_HS200,
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SD_EMMC_EMMC_HS400,
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SD_EMMC_EMMC_HS300,
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} timing;
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} emmc_config;
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uint8_t xhci0_force_gen1;
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@ -13,7 +13,7 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
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{
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int val = SD_DISABLE;
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switch (cfg->sd_emmc_config) {
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switch (cfg->emmc_config.timing) {
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case SD_EMMC_DISABLE:
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val = SD_DISABLE;
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break;
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