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sb/intel/bd82x6x/sata: Clean up IDE modes 

Don't set legacy timing values that don't affect the hardware but
enable the OOB retry mode as already done on the AHCI path.

Change-Id: I0b078d7790ca801a89066ef6a161d900be5eb778
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber 2019-02-28 12:43:21 +01:00 committed by Angel Pons
parent 14929253a5
commit 56473ca9a7
1 changed files with 5 additions and 17 deletions
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22
src/southbridge/intel/bd82x6x/sata.c
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@ -187,26 +187,14 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n"); printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n");
} }
/* Set timings */ /* Enable I/O decoding */
pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
IDE_PPE0 | IDE_IE0 | IDE_TIME0);
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
IDE_SITRE | IDE_ISP_3_CLOCKS |
IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
/* Sync DMA */ /* Port enable + OOB retry mode */
pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Port enable */
reg16 = pci_read_config16(dev, 0x92); reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f; reg16 &= ~0x3f;
reg16 |= config->sata_port_map; reg16 |= config->sata_port_map | 0x8000;
pci_write_config16(dev, 0x92, reg16); pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ /* SATA Initialization register */