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Following patch extends the ROM decoding to last 1MB, allowing to use larger 

flashes such as SST49LF080A: 1024K x8 (8 Mbit)

Tested on my system, the flash is found and if I use coreboot in second half it
works too.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2008-03-15 00:26:50 +00:00
parent dd52e17448
commit 5671787b9e
2 changed files with 17 additions and 0 deletions
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2
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
View File

@ -192,6 +192,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();
print_info("now booting... fallback\r\n");
@ -259,6 +260,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();
print_info("now booting... real_main\r\n");

15
src/southbridge/via/vt8237r/vt8237r_early_smbus.c
View File

@ -212,3 +212,18 @@ void smbus_fixup(const struct mem_controller *ctrl)
else
PRINT_DEBUG("Done\r\n");
}
void enable_rom_decode(void)
{
device_t dev;
/* Bus Control and Power Management */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("SB not found\r\n");
/* ROM decode last 1MB FFC00000 - FFFFFFFF */
pci_write_config8(dev, 0x41, 0x7f);
}