intel/baytrail: Use smm_subregion()
Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34739 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -88,13 +88,12 @@ static const struct cpu_driver driver __cpu_driver = {
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* MP and SMM loading initialization.
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* MP and SMM loading initialization.
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*/
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*/
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struct smm_relocation_attrs {
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struct smm_relocation_params {
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uint32_t smbase;
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msr_t smrr_base;
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uint32_t smrr_base;
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msr_t smrr_mask;
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uint32_t smrr_mask;
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};
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};
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static struct smm_relocation_attrs relo_attrs;
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static struct smm_relocation_params smm_reloc_params;
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/* Package level MSRs */
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/* Package level MSRs */
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static const struct reg_script package_msr_script[] = {
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static const struct reg_script package_msr_script[] = {
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@ -140,20 +139,32 @@ static int get_cpu_count(void)
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return pattrs->num_cpus;
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return pattrs->num_cpus;
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}
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}
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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uintptr_t tseg_base;
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size_t tseg_size;
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/* All range registers are aligned to 4KiB */
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const u32 rmask = ~((1 << 12) - 1);
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smm_region(&tseg_base, &tseg_size);
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
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params->smrr_base.hi = 0;
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params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
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params->smrr_mask.hi = 0;
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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size_t *smm_save_state_size)
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{
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{
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/* All range registers are aligned to 4KiB */
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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const uint32_t rmask = ~((1 << 12) - 1);
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/* Initialize global tracking state. */
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fill_in_relocation_params(&smm_reloc_params);
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relo_attrs.smbase = (uint32_t)smm_region_start();
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relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask;
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relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
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*perm_smbase = relo_attrs.smbase;
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*perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE;
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*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
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*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
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}
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}
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@ -179,16 +190,12 @@ static void per_cpu_smm_trigger(void)
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static void relocation_handler(int cpu, uintptr_t curr_smbase,
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static void relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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uintptr_t staggered_smbase)
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{
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{
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msr_t smrr;
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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em64t100_smm_state_save_area_t *smm_state;
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em64t100_smm_state_save_area_t *smm_state;
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/* Set up SMRR. */
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/* Set up SMRR. */
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smrr.lo = relo_attrs.smrr_base;
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wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
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smrr.hi = 0;
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wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
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wrmsr(IA32_SMRR_PHYS_BASE, smrr);
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smrr.lo = relo_attrs.smrr_mask;
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smrr.hi = 0;
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wrmsr(IA32_SMRR_PHYS_MASK, smrr);
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smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
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smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
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smm_state->smbase = staggered_smbase;
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smm_state->smbase = staggered_smbase;
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@ -18,19 +18,6 @@
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#include <types.h>
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#include <types.h>
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/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
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* is included after chipset code. This causes the chipset's Kconfig to be
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* clobbered by the arch/x86/Kconfig if they have the same name. */
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static inline int smm_region_size(void)
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{
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/* Make it 8MiB by default. */
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if (CONFIG_SMM_TSEG_SIZE == 0)
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return (8 << 20);
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return CONFIG_SMM_TSEG_SIZE;
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}
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uintptr_t smm_region_start(void);
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enum {
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enum {
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SMM_SAVE_PARAM_GPIO_ROUTE = 0,
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SMM_SAVE_PARAM_GPIO_ROUTE = 0,
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SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
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SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
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@ -14,29 +14,26 @@
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*/
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*/
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#include <cbmem.h>
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#include <cbmem.h>
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#include <stage_cache.h>
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#include <cpu/x86/smm.h>
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#include <soc/iosf.h>
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#include <soc/iosf.h>
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#include <soc/smm.h>
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uintptr_t smm_region_start(void)
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static uintptr_t smm_region_start(void)
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{
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{
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return (iosf_bunit_read(BUNIT_SMRRL) << 20);
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return (iosf_bunit_read(BUNIT_SMRRL) << 20);
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}
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}
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static size_t smm_region_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void *cbmem_top(void)
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void *cbmem_top(void)
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{
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{
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return (void *) smm_region_start();
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return (void *) smm_region_start();
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}
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}
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void stage_cache_external_region(void **base, size_t *size)
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void smm_region(uintptr_t *start, size_t *size)
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{
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{
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char *smm_base;
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*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
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/* 1MiB cache size */
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*size = smm_region_size();
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const long cache_size = CONFIG_SMM_RESERVED_SIZE;
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/* Ramstage cache lives in TSEG region which is the definition of
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* cbmem_top(). */
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smm_base = cbmem_top();
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*size = cache_size;
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*base = &smm_base[smm_region_size() - cache_size];
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}
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}
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@ -30,7 +30,6 @@
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#include <elog.h>
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#include <elog.h>
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#include <program_loading.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <romstage_handoff.h>
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#include <stage_cache.h>
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#include <string.h>
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#include <string.h>
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#include <timestamp.h>
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#include <timestamp.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -41,7 +40,6 @@
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/pmc.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <soc/smm.h>
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#include <soc/spi.h>
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#include <soc/spi.h>
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static void program_base_addresses(void)
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static void program_base_addresses(void)
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