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mb/google/poppy/variants/atlas: Revise AC/DC loadline 

This patch revises the AC/DC loadline settings because some major
layout changes between proto and evt boards.

BUG=b:130740639
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS.

Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
This commit is contained in:
Gaggery Tsai 2019-04-18 08:54:38 -07:00 committed by Patrick Georgi
parent a11553dabd
commit 56d66ae854
1 changed files with 9 additions and 9 deletions
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18
src/mainboard/google/poppy/variants/atlas/devicetree.cb
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@ -88,8 +88,8 @@ chip soc/intel/skylake
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | set by SoC code per CPU SKU |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 14.75 | 4.42 | 4.7 | 4.7 |
#| DcLoadline | 14.2 | 4.2 | 4.41 | 4.41 |
#| AcLoadline | 16.20 | 5.24 | 4.62 | 4.62 |
#| DcLoadline | 14.2 | 4.94 | 4.25 | 4.25 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
@ -101,7 +101,7 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
.ac_loadline = 1475,
.ac_loadline = 1620,
.dc_loadline = 1420,
}"
@ -115,8 +115,8 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
.ac_loadline = 442,
.dc_loadline = 420,
.ac_loadline = 524,
.dc_loadline = 494,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
@ -129,8 +129,8 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
.ac_loadline = 470,
.dc_loadline = 441,
.ac_loadline = 462,
.dc_loadline = 425,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
@ -143,8 +143,8 @@ chip soc/intel/skylake
.imon_slope = 0x0,
.imon_offset = 0x0,
.voltage_limit = 1520,
.ac_loadline = 470,
.dc_loadline = 441,
.ac_loadline = 462,
.dc_loadline = 425,
}"
# PCIe Root port 1 with SRCCLKREQ1# (WLAN)