x86: unify amd and non-amd MTRR routines

The amd_mtrr.c file contains a copy of the fixed MTRR algorithm.
However, the AMD code needs to handle the RdMem and WrMem attribute
bits in the fixed MTRR MSRs. Instead of duplicating the code
with the one slight change introduce a Kconfig option,
X86_AMD_FIXED_MTRRS, which indicates that the RdMem and WrMem fields
need to be handled for writeback fixed MTRR ranges.

The order of how the AMD MTRR setup routine is maintained by providing
a x86_setup_fixed_mtrrs_no_enable() function which does not enable
the fixed MTRRs after setting them up. All Kconfig files which had a
Makefile that included amd/mtrr in the subdirs-y now have a default
X86_AMD_FIXED_MTRRS selection. There may be some overlap with the
agesa and socket code, but I didn't know the best way to tease out
the interdependency.

Change-Id: I256d0210d1eb3004e2043b46374dcc0337432767
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2866
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

src/cpu/amd/agesa/family10/Kconfig

@@ -21,6 +21,7 @@ config CPU_AMD_AGESA_FAMILY10
 	bool
 	select CPU_AMD_MODEL_10XXX
 	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
 
 if CPU_AMD_AGESA_FAMILY10
 

src/cpu/amd/agesa/family12/Kconfig

@@ -20,6 +20,7 @@
 config CPU_AMD_AGESA_FAMILY12
 	bool
 	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_ADDR_BITS
 	int

src/cpu/amd/agesa/family14/Kconfig

@@ -20,6 +20,7 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_ADDR_BITS
 	int

src/cpu/amd/agesa/family15/Kconfig

@@ -20,6 +20,7 @@
 config CPU_AMD_AGESA_FAMILY15
 	bool
 	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_ADDR_BITS
 	int

src/cpu/amd/agesa/family15tn/Kconfig

@@ -20,6 +20,7 @@
 config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select PCI_IO_CFG_EXT
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_ADDR_BITS
 	int

src/cpu/amd/mtrr/amd_mtrr.c

@@ -6,102 +6,6 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 
-static unsigned long resk(uint64_t value)
-{
-	unsigned long resultk;
-	if (value < (1ULL << 42)) {
-		resultk = value >> 10;
-	}
-	else {
-		resultk = 0xffffffff;
-	}
-	return resultk;
-}
-
-static unsigned fixed_mtrr_index(unsigned long addrk)
-{
-	unsigned index;
-	index = (addrk - 0) >> 6;
-	if (index >= 8) {
-		index = ((addrk - 8*64) >> 4) + 8;
-	}
-	if (index >= 24) {
-		index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
-	}
-	if (index > NUM_FIXED_RANGES) {
-		index = NUM_FIXED_RANGES;
-	}
-	return index;
-}
-
-static unsigned int mtrr_msr[] = {
-	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
-	MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
-	MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
-};
-
-static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
-{
-	unsigned int i;
-	unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
-	msr_t msr;
-	msr.lo = msr.hi = 0; /* Shut up gcc */
-	for (i = first; i < last; i++) {
-		/* When I switch to a new msr read it in */
-		if (fixed_msr != i >> 3) {
-			/* But first write out the old msr */
-			if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
-				disable_cache();
-				wrmsr(mtrr_msr[fixed_msr], msr);
-				enable_cache();
-			}
-			fixed_msr = i>>3;
-			msr = rdmsr(mtrr_msr[fixed_msr]);
-		}
-		if ((i & 7) < 4) {
-			msr.lo &= ~(0xff << ((i&3)*8));
-			msr.lo |= type << ((i&3)*8);
-		} else {
-			msr.hi &= ~(0xff << ((i&3)*8));
-			msr.hi |= type << ((i&3)*8);
-		}
-	}
-	/* Write out the final msr */
-	if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
-		disable_cache();
-		wrmsr(mtrr_msr[fixed_msr], msr);
-		enable_cache();
-	}
-}
-
-struct mem_state {
-	unsigned long tomk, tom2k;
-};
-static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
-{
-	struct mem_state *state = gp;
-	unsigned long topk;
-	unsigned int start_mtrr;
-	unsigned int last_mtrr;
-
-	topk = resk(res->base + res->size);
-	if (state->tom2k < topk) {
-		state->tom2k = topk;
-	}
-	if ((topk < 4*1024*1024) && (state->tomk < topk)) {
-		state->tomk = topk;
-	}
-	start_mtrr = fixed_mtrr_index(resk(res->base));
-	last_mtrr  = fixed_mtrr_index(resk((res->base + res->size)));
-	if (start_mtrr >= NUM_FIXED_RANGES) {
-		return;
-	}
-	printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
-		start_mtrr, last_mtrr);
-	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
-
-}
-
 /* These will likely move to some device node or cbmem. */
 static uint64_t amd_topmem = 0;
 static uint64_t amd_topmem2 = 0;
@@ -162,7 +66,6 @@ static void setup_ap_ramtop(void)
 void amd_setup_mtrrs(void)
 {
 	unsigned long address_bits;
-	struct mem_state state;
 	unsigned long i;
 	msr_t msr, sys_cfg;
 	// Test if this CPU is a Fam 0Fh rev. F or later
@@ -182,18 +85,8 @@ void amd_setup_mtrrs(void)
 	wrmsr(SYSCFG_MSR, sys_cfg);
 	enable_cache();
 
-	printk(BIOS_DEBUG, "\n");
+	/* Setup fixed MTRRs, but do not enable them just yet. */
-	/* Initialized the fixed_mtrrs to uncached */
+	x86_setup_fixed_mtrrs_no_enable();
-	printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
-		0, NUM_FIXED_RANGES);
-	set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
-
-	state.tomk = state.tom2k = 0;
-	search_global_resources(
-		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
-		set_fixed_mtrr_resource, &state);
-
-	printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
 
 	disable_cache();
 

src/cpu/amd/socket_754/Kconfig

@@ -7,6 +7,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_ADDR_BITS
 	int

src/cpu/amd/socket_939/Kconfig

@@ -2,4 +2,5 @@ config CPU_AMD_SOCKET_939
 	bool
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 

src/cpu/amd/socket_940/Kconfig

@@ -8,6 +8,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_ADDR_BITS
 	int

src/cpu/amd/socket_AM2/Kconfig

@@ -5,6 +5,7 @@ config CPU_AMD_SOCKET_AM2
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_AM2r2/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_AM2R2
 	select HT3_SUPPORT
 	select PCI_IO_CFG_EXT
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_AM3/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_AM3
 	select HT3_SUPPORT
 	select PCI_IO_CFG_EXT
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_ASB2/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_ASB2
 	select HT3_SUPPORT
 	select PCI_IO_CFG_EXT
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_C32/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_C32_NON_AGESA
 	select HT3_SUPPORT
 	select PCI_IO_CFG_EXT
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_F/Kconfig

@@ -4,6 +4,7 @@ config CPU_AMD_SOCKET_F
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_F_1207/Kconfig

@@ -3,6 +3,7 @@ config CPU_AMD_SOCKET_F_1207
 	select CPU_AMD_MODEL_10XXX
 	select PCI_IO_CFG_EXT
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/amd/socket_S1G1/Kconfig

@@ -9,6 +9,7 @@ config SOCKET_SPECIFIC_OPTIONS
 	select K8_HT_FREQ_1G_SUPPORT
 	select CPU_AMD_MODEL_FXX
 	select CACHE_AS_RAM
+	select X86_AMD_FIXED_MTRRS
 
 config CPU_SOCKET_TYPE
 	hex

src/cpu/x86/Kconfig

@@ -84,3 +84,10 @@ config SMM_MODULE_HEAP_SIZE
 	help
 	  This option determines the size of the heap within the SMM handler
 	  modules.
+
+config X86_AMD_FIXED_MTRRS
+	bool
+	default n
+	help
+	  This option informs the MTRR code to use the RdMem and WrMem fields
+	  in the fixed MTRR MSRs.

src/cpu/x86/mtrr/mtrr.c

@@ -39,6 +39,12 @@
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
 #include <arch/acpi.h>
+#if CONFIG_X86_AMD_FIXED_MTRRS
+#include <cpu/amd/mtrr.h>
+#define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)
+#else
+#define MTRR_FIXED_WRBACK_BITS 0
+#endif
 
 static unsigned int mtrr_msr[] = {
 	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
@@ -325,6 +331,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
 {
 	unsigned int start_mtrr;
 	unsigned int last_mtrr;
+	const unsigned char type = MTRR_TYPE_WRBACK | MTRR_FIXED_WRBACK_BITS;
 	start_mtrr = fixed_mtrr_index(resk(res->base));
 	last_mtrr  = fixed_mtrr_index(resk((res->base + res->size)));
 	if (start_mtrr >= NUM_FIXED_RANGES) {
@@ -332,7 +339,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
 	}
 	printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n",
 		start_mtrr, last_mtrr);
-	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
+	set_fixed_mtrrs(start_mtrr, last_mtrr, type);
 
 }
 
@@ -406,7 +413,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 	state->range_sizek  = sizek;
 }
 
-void x86_setup_fixed_mtrrs(void)
+void x86_setup_fixed_mtrrs_no_enable(void)
 {
         /* Try this the simple way of incrementally adding together
          * mtrrs.  If this doesn't work out we can get smart again
@@ -425,13 +432,17 @@ void x86_setup_fixed_mtrrs(void)
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_fixed_mtrr_resource, NULL);
         printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
-
-        /* enable fixed MTRR */
-        printk(BIOS_SPEW, "call enable_fixed_mtrr()\n");
-        enable_fixed_mtrr();
-
 }
 
+void x86_setup_fixed_mtrrs(void)
+{
+	x86_setup_fixed_mtrrs_no_enable();
+
+	printk(BIOS_SPEW, "call enable_fixed_mtrr()\n");
+	enable_fixed_mtrr();
+}
+
+
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 /* this routine needs to know how many address bits a given processor
  * supports.  CPUs get grumpy when you set too many bits in
@@ -500,7 +511,6 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	post_code(0x6A);
 }
 
-
 void x86_setup_mtrrs(void)
 {
 	int address_size;
@@ -510,7 +520,6 @@ void x86_setup_mtrrs(void)
 	x86_setup_var_mtrrs(address_size, 1);
 }
 
-
 int x86_mtrr_check(void)
 {
 	/* Only Pentium Pro and later have MTRR */

src/include/cpu/x86/mtrr.h

@@ -53,6 +53,8 @@ void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);
+/* Set up fixed MTRRs but do not enable them. */
+void x86_setup_fixed_mtrrs_no_enable(void);
 #endif
 
 #if !defined(CONFIG_RAMTOP)