nb/intel/sandybridge: Put host bridge registers into its own file
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Ibfaecd6ab94d2caae9804bb827ce8e48a2166d35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SANDYBRIDGE_HOSTBRIDGE_REGS_H__
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#define __SANDYBRIDGE_HOSTBRIDGE_REGS_H__
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_PEG60 (1 << 13)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_IGD (1 << 4)
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#define DEVEN_PEG10 (1 << 3)
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#define DEVEN_PEG11 (1 << 2)
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#define DEVEN_PEG12 (1 << 1)
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#define DEVEN_HOST (1 << 0)
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#define PAVPC 0x58 /* Protected Audio Video Path Control */
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#define DPR 0x5c /* DMA Protected Range */
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define MESEG_BASE 0x70
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#define MESEG_MASK 0x78
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#define MELCK (1 << 10) /* ME Range Lock */
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#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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#define LAC 0x87 /* Legacy Access Control */
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#define SMRAM 0x88 /* System Management RAM Control */
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#define REMAPBASE 0x90
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#define REMAPLIMIT 0x98
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#define TOM 0xa0
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#define BDSM 0xb0 /* Base Data of Stolen Memory */
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEGMB 0xb8 /* TSEG Memory Base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define CAPID0_A 0xe4 /* Capabilities Register A */
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#define CAPID0_B 0xe8 /* Capabilities Register B */
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#define SKPAD 0xdc /* Scratchpad Data */
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#define DIDOR 0xf3 /* Device ID override, for debug and samples only */
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#endif /* __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ */
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@ -48,57 +48,7 @@ enum platform_type {
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_PEG60 (1 << 13)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_IGD (1 << 4)
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#define DEVEN_PEG10 (1 << 3)
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#define DEVEN_PEG11 (1 << 2)
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#define DEVEN_PEG12 (1 << 1)
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#define DEVEN_HOST (1 << 0)
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#define PAVPC 0x58 /* Protected Audio Video Path Control */
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#define DPR 0x5c /* DMA Protected Range */
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define MESEG_BASE 0x70
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#define MESEG_MASK 0x78
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#define MELCK (1 << 10) /* ME Range Lock */
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#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */
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#define PAM0 0x80
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#define PAM1 0x81
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#define PAM2 0x82
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#define PAM3 0x83
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#define PAM4 0x84
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#define PAM5 0x85
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#define PAM6 0x86
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#define LAC 0x87 /* Legacy Access Control */
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#define SMRAM 0x88 /* System Management RAM Control */
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#define REMAPBASE 0x90
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#define REMAPLIMIT 0x98
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#define TOM 0xa0
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#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
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#define BDSM 0xb0 /* Base Data of Stolen Memory */
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEGMB 0xb8 /* TSEG Memory Base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define CAPID0_A 0xe4 /* Capabilities Register A */
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#define CAPID0_B 0xe8 /* Capabilities Register B */
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#define SKPAD 0xdc /* Scratchpad Data */
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#define DIDOR 0xf3 /* Device ID override, for debug and samples only */
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#include "hostbridge_regs.h"
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/* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */
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