Drop excessive whitespace randomly sprinkled in romstage.c files.

Also drop some dead or useless code snippets.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/advantech/pcm-5820/romstage.c

@@ -42,4 +42,3 @@ static void main(unsigned long bist)
 	sdram_init();
 	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/amd/db800/romstage.c

@@ -31,13 +31,12 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
@@ -96,4 +95,3 @@ void main(unsigned long bist)
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
-

src/mainboard/amd/dbm690t/romstage.c

@@ -31,24 +31,18 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <spd.h>
-
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
@@ -75,16 +69,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -188,4 +176,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/amd/mahogany/romstage.c

@@ -32,22 +32,17 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
@@ -74,16 +69,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -186,4 +175,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -38,22 +38,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -71,18 +65,14 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
@@ -247,4 +237,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-

src/mainboard/amd/norwich/romstage.c

@@ -31,7 +31,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -97,4 +96,3 @@ void main(unsigned long bist)
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
-

src/mainboard/amd/pistachio/romstage.c

@@ -26,23 +26,18 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
 #include <spd.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
@@ -69,16 +64,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -199,4 +188,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/amd/rumba/romstage.c

@@ -10,12 +10,11 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
  	if (device != DIMM0)
@@ -61,4 +60,3 @@ void main(unsigned long bist)
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }
-

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -11,32 +11,25 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include <reset.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
 	//GPIO on amd8111 to enable MEMRST ????
@@ -87,27 +80,20 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
 
 #define RC0 ((1<<0)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<2)<<8)
 #define RC3 ((1<<3)<<8)
 
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "cpu/amd/model_fxx/fidvid.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -283,6 +269,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -40,25 +40,17 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
 #include <spd.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk(BIOS_EMERG, fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
-#endif
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 static void memreset_setup(void)
 {
@@ -91,18 +83,14 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -201,7 +189,6 @@ static const u8 spd_addr[] = {
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	u32 bsp_apicid = 0;
 	u32 val;
@@ -353,6 +340,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
-
 }
-

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -38,22 +38,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -70,18 +64,14 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>

src/mainboard/arima/hdama/romstage.c

@@ -7,29 +7,24 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87360/pc87360_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -68,18 +63,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -154,4 +144,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/artecgroup/dbe61/romstage.c

@@ -33,7 +33,6 @@
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -145,4 +144,3 @@ void main(unsigned long bist)
 	// ram_check(0x00000000, 640 * 1024);
 	// ram_check(1024 * 1024, 2 * 1024 * 1024);
 }
-

src/mainboard/asi/mb_5blgp/romstage.c

@@ -42,4 +42,3 @@ static void main(unsigned long bist)
 	sdram_init();
 	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/asrock/939a785gmh/romstage.c

@@ -32,23 +32,18 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
@@ -79,16 +74,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_init(void)
@@ -106,7 +95,6 @@ static void sio_init(void)
 	pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
 	pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
 
-
 //idx 30 e0 e1 e2 e3 e4 e5 e6  e7 e8 e9 f0 f1 f2 f3 f4  f5 f6 f7 fe
 //val 07 XX XX XX f6 0e 00 00  00 00 ff d6 96 00 40 d0  83 00 00 07
 
@@ -240,4 +228,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/asus/a8n_e/romstage.c

@@ -69,10 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -168,4 +166,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -86,15 +86,12 @@ void soft_reset(void)
 
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -232,4 +229,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
-

src/mainboard/asus/a8v-e_se/romstage.c

@@ -86,15 +86,12 @@ void soft_reset(void)
 
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -232,4 +229,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
-

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -69,15 +69,12 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
 
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
@@ -202,4 +199,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
-

src/mainboard/asus/m2v/romstage.c

@@ -71,15 +71,12 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
 
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -304,4 +301,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
-

src/mainboard/asus/m4a785-m/romstage.c

@@ -38,22 +38,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -70,18 +64,14 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>

src/mainboard/axus/tc320/romstage.c

@@ -43,4 +43,3 @@ static void main(unsigned long bist)
 	sdram_init();
 	/* ram_check(0, 640 * 1024); */
 }
-

src/mainboard/broadcom/blast/romstage.c

@@ -7,7 +7,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
@@ -15,22 +14,18 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
 
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
 static void memreset_setup(void)
 {
 }
@@ -65,22 +60,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "northbridge/amd/amdk8/early_ht.c"
 
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "northbridge/amd/amdk8/early_ht.c"
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -184,6 +173,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
 	post_cache_as_ram();
-
 }
-

src/mainboard/dell/s1850/romstage.c

@@ -343,11 +343,4 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-
-#if 0
-	while(1) {
-		hlt();
-	}
-#endif
 }
-

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -63,7 +63,6 @@ void main(unsigned long bist)
 #endif
 
 		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-
 	}
 
 #if 0
@@ -78,4 +77,3 @@ void main(unsigned long bist)
 	ram_check(0x80000000, 0x81000000);
 #endif
 }
-

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -8,7 +8,6 @@
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
-//#include "lib/delay.c"
 
 void setup_pars(void)
 {
@@ -48,8 +47,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 //	return smbus_read_byte(device, address);
 }
 
-//#include "lib/generic_sdram.c"
-
 static inline void dumpmem(void){
   int i, j;
   unsigned char *l;
@@ -251,4 +248,3 @@ static void main(unsigned long bist)
 	while(1);
 #endif
 }
-

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -12,13 +12,12 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 		return smbus_read_byte(device, address);
@@ -27,6 +26,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define ManualConf 0		/* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
+
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
@@ -97,4 +97,3 @@ void main(unsigned long bist)
 	void done_cache_as_ram_main(void);
 	done_cache_as_ram_main();
 }
-

src/mainboard/eaglelion/5bcm/romstage.c

@@ -7,18 +7,13 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
-//#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
-//#include "northbridge/intel/i440bx/raminit.h"
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "northbridge/amd/gx1/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
-//#include "lib/delay.c"
-
-#include "northbridge/amd/gx1/raminit.c"
-
 static void main(unsigned long bist)
 {
 	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -53,4 +48,3 @@ static void main(unsigned long bist)
 	}
 #endif
 }
-

src/mainboard/getac/p470/romstage.c

@@ -28,12 +28,9 @@
 #include <cpu/x86/lapic.h>
 #include <lib.h>
 #include <usbdebug.h>
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -100,7 +97,6 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
 }
 
-
 /* This box has two superios, so enabling serial becomes slightly excessive.
  * We disable a lot of stuff to make sure that there are no conflicts between
  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
@@ -398,4 +394,3 @@ void main(unsigned long bist)
 	}
 #endif
 }
-

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -34,37 +34,28 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/sis/sis966/sis966.h"
 #include "southbridge/sis/sis966/sis966_early_smbus.c"
 #include "southbridge/sis/sis966/sis966_enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/sis/sis966/sis966_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
-#include "southbridge/sis/sis966/sis966_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -84,9 +75,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 
 #define SIS966_NUM 1
@@ -104,13 +93,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
 #include "southbridge/sis/sis966/sis966_early_setup_ss.h"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -205,7 +190,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
 #if CONFIG_SET_FIDVID
-
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
@@ -252,6 +236,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         sis_init_stage2();
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/gigabyte/m57sli/romstage.c

@@ -32,36 +32,27 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -86,25 +77,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -214,7 +196,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
 #if CONFIG_SET_FIDVID
-
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
@@ -260,6 +241,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -34,22 +34,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -66,25 +60,20 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0;

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -38,22 +38,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -70,25 +64,20 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0;
@@ -129,7 +118,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	console_init();
 	printk(BIOS_DEBUG, "\n");
 
-
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -247,4 +235,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-

src/mainboard/hp/dl145_g1/romstage.c

@@ -7,29 +7,23 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -90,20 +84,15 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
-#define RC0 ((1<<1)<<8) // Not sure about these values
-#define RC1 ((1<<2)<<8) // Not sure about these values
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
+#define RC0 ((1<<1)<<8) // Not sure about these values
+#define RC1 ((1<<2)<<8) // Not sure about these values
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {

src/mainboard/hp/dl145_g3/romstage.c

@@ -38,37 +38,27 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "superio/serverengines/pilot/pilot_early_serial.c"
 #include "superio/serverengines/pilot/pilot_early_init.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
 
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -93,15 +83,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
 #include <spd.h>
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 #if 0
@@ -248,4 +233,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -45,29 +45,22 @@
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
 #include <spd.h>
-
 #include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include "superio/serverengines/pilot/pilot_early_serial.c"
 #include "superio/serverengines/pilot/pilot_early_init.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
 
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	u8 val;
@@ -85,18 +78,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 
 static const u8 spd_addr[] = {
@@ -113,7 +101,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo =  (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-
 	u32 bsp_apicid = 0;
 	u32 val;
 	msr_t msr;

src/mainboard/ibase/mb899/romstage.c

@@ -27,23 +27,18 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
-
 #include "superio/winbond/w83627ehg/w83627ehg.h"
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/x86/bist.h>
-
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
+#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+
 void enable_smbus(void);
 
 void setup_ich7_gpios(void)
@@ -358,4 +353,3 @@ void main(unsigned long bist)
 	}
 #endif
 }
-

src/mainboard/ibm/e325/romstage.c

@@ -8,29 +8,24 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87366/pc87366_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
@@ -64,18 +59,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -148,6 +138,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
-
 }
-

src/mainboard/ibm/e326/romstage.c

@@ -8,29 +8,24 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87366/pc87366_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 #include <spd.h>
 
+#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
+
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
@@ -64,18 +59,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -148,6 +138,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
-
 }
-

src/mainboard/iei/juki-511p/romstage.c

@@ -30,11 +30,10 @@
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
+#include "northbridge/amd/gx1/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 
-#include "northbridge/amd/gx1/raminit.c"
-
 static void main(unsigned long bist)
 {
 	/* Initialize the serial console. */
@@ -57,4 +56,3 @@ static void main(unsigned long bist)
 	/* Check RAM. */
 	/* ram_check(0x00000000, 640 * 1024); */
 }
-

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -41,22 +41,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/fintek/f71859/f71859_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -73,18 +67,14 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
@@ -250,4 +240,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-

src/mainboard/iei/nova4899r/romstage.c

@@ -52,4 +52,3 @@ static void main(unsigned long bist)
 	/* Check RAM. */
 	/* ram_check(0x00000000, 640 * 1024); */
 }
-

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -31,13 +31,12 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
@@ -99,4 +98,3 @@ void main(unsigned long bist)
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
-

src/mainboard/intel/d945gclf/romstage.c

@@ -27,23 +27,18 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
-
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/x86/bist.h>
-
 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
 void enable_smbus(void);
 
 void setup_ich7_gpios(void)
@@ -317,4 +312,3 @@ void main(unsigned long bist)
 	}
 #endif
 }
-

src/mainboard/intel/eagleheights/romstage.c

@@ -21,20 +21,16 @@
  */
 
 #include <delay.h>
-
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/acpi.h>
-
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
@@ -196,4 +192,3 @@ void main(unsigned long bist)
 	/* Initialize memory */
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 }
-

src/mainboard/intel/jarrell/romstage.c

@@ -63,6 +63,7 @@ static void main(unsigned long bist)
 			skip_romstage();
 		}
 	}
+
 	/* Setup the console */
 	pc87427_disable_dev(CONSOLE_SERIAL_DEV);
 	pc87427_disable_dev(HIDDEN_SERIAL_DEV);
@@ -127,11 +128,5 @@ static void main(unsigned long bist)
 	ram_check(0x00000000, 0x02000000);
 #endif
 
-#endif
-#if 0
-	while(1) {
-		hlt();
-	}
 #endif
 }
-

src/mainboard/intel/mtarvon/romstage.c

@@ -15,7 +15,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
  */
 
 #include <stdint.h>
@@ -122,4 +121,3 @@ void main(unsigned long bist)
 
 	ram_check(0, 1024 * 1024);
 }
-

src/mainboard/intel/truxton/romstage.c

@@ -105,4 +105,3 @@ static void main(unsigned long bist)
 	ram_verify(0x00000000, 0x02000000);
 #endif
 }
-

src/mainboard/intel/xe7501devkit/romstage.c

@@ -78,4 +78,3 @@ static void main(unsigned long bist)
 	//		 if the following line is removed.
 	print_debug("SDRAM is up.\n");
 }
-

src/mainboard/iwill/dk8_htx/romstage.c

@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -212,6 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/iwill/dk8s2/romstage.c

@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
+#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "northbridge/amd/amdk8/resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -212,6 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/iwill/dk8x/romstage.c

@@ -11,30 +11,23 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-
 #include "cpu/x86/bist.h"
-
 #include "lib/delay.c"
-
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 /*
  * GPIO28 of 8111 will control H0_MEMRESET_L
  * GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
+#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "northbridge/amd/amdk8/resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -212,6 +198,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/jetway/j7f24/romstage.c

@@ -111,4 +111,3 @@ void main(unsigned long bist)
 
 	print_spew("Leaving romstage.c:main()\n");
 }
-

src/mainboard/jetway/pa78vm5/romstage.c

@@ -39,64 +39,50 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/fintek/f71863fg/f71863fg_early_serial.c"
+#include <usbdebug.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/rs780_early_setup.c"
+#include "southbridge/amd/sb700/sb700_early_setup.c"
+#include "northbridge/amd/amdfam10/debug.c"
+
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2)
 #else
 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
 #endif
 
-#include <usbdebug.h>
-
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include <cpu/amd/mtrr.h>
-#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
-#include "southbridge/amd/rs780/rs780_early_setup.c"
-#include "southbridge/amd/sb700/sb700_early_setup.c"
-#include "northbridge/amd/amdfam10/debug.c"
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-	int result;
+	return smbus_read_byte(device, address);
-	result = smbus_read_byte(device, address);
-	return result;
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
 	u32 bsp_apicid = 0;
@@ -255,4 +241,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-

src/mainboard/kontron/986lcd-m/romstage.c

@@ -28,25 +28,19 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <usbdebug.h>
-
 #include "superio/winbond/w83627thg/w83627thg.h"
-
 #include <pc80/mc146818rtc.h>
 #include "option_table.h"
-
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
 void enable_smbus(void);
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
 void setup_ich7_gpios(void)
 {
 	printk(BIOS_DEBUG, " GPIOS...");
@@ -454,4 +448,3 @@ void main(unsigned long bist)
 	}
 #endif
 }
-

src/mainboard/kontron/kt690/romstage.c

@@ -32,25 +32,19 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
-
 #include <usbdebug.h>
-
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 
@@ -76,16 +70,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -191,4 +179,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/lippert/frontrunner/romstage.c

@@ -11,12 +11,11 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static const unsigned char spdbytes[] = {	/* 4x Qimonda HYB25DC512160CF-6 */
 	0xFF, 0xFF,				/* only values used by raminit.c are set */
 	[SPD_MEMORY_TYPE]		= SPD_MEMORY_TYPE_SDRAM_DDR,	/* (Fundamental) memory type */
@@ -131,6 +130,4 @@ void main(unsigned long bist)
 //	ram_check(0, 16384);
 	ram_check(0x20000, 0x24000);
 //	ram_check(0x00000000, 640*1024);
-
 }
-

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -34,7 +34,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"

src/mainboard/lippert/literunner-lx/romstage.c

@@ -34,7 +34,6 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -34,7 +34,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -34,7 +34,6 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"

src/mainboard/msi/ms7135/romstage.c

@@ -22,8 +22,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -35,7 +33,6 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -51,6 +48,8 @@
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
 
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 	/* FIXME: Nothing to do? */
@@ -70,10 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -171,4 +168,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/msi/ms7260/romstage.c

@@ -33,7 +33,6 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/amd/model_fxx_rev.h>
@@ -43,22 +42,18 @@
 #include "lib/delay.c"
 #include <lib.h>
 #include <spd.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
-/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
-#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
+#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl) {}
 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
 
@@ -72,7 +67,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -86,11 +80,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -233,4 +225,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* bsp switch stack to RAM and copy sysinfo RAM now. */
 	post_cache_as_ram();
 }
-

src/mainboard/msi/ms9185/romstage.c

@@ -33,7 +33,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
@@ -41,19 +40,17 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <reset.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
@@ -88,24 +85,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* msi does not want the default */
- /* msi does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "cpu/amd/model_fxx/fidvid.c"
+#include "northbridge/amd/amdk8/early_ht.c"
 
 #define RC0 (0x10<<8)
 #define RC1 (0x01<<8)
 
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "cpu/amd/model_fxx/fidvid.c"
-
-#include "northbridge/amd/amdk8/early_ht.c"
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -260,6 +250,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        post_cache_as_ram();
-
 }
-

src/mainboard/msi/ms9282/romstage.c

@@ -31,29 +31,24 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include <spd.h>
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
 #include <device/pci_ids.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -87,12 +82,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* msi does not want the default */
- /* msi does not want the default */
-#include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+
 //set GPIO to input mode
 #define MCP55_MB_SETUP \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
@@ -101,13 +94,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
 // Disabled until it's actually used:
 // #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -210,4 +200,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -34,31 +34,23 @@
 #include <usbdebug.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_10xxx_rev.h>
-
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -70,12 +62,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
 
 #define MCP55_MB_SETUP \
@@ -88,16 +77,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -277,4 +260,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-

src/mainboard/newisys/khepri/romstage.c

@@ -15,29 +15,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
 	if (is_cpu_pre_c0()) {
@@ -72,22 +66,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* newisys khepri does not want the default */
- /* newisys khepri does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -171,6 +156,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
 	post_cache_as_ram();
-
 }
-

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -32,36 +32,27 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -81,9 +72,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 
 #define MCP55_MB_SETUP \
@@ -96,15 +85,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -245,6 +228,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 	post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/pcengines/alix1c/romstage.c

@@ -187,4 +187,3 @@ void main(unsigned long bist)
 	void done_cache_as_ram_main(void);
 	done_cache_as_ram_main();
 }
-

src/mainboard/pcengines/alix2d/romstage.c

@@ -136,8 +136,6 @@ static void mb_gpio_init(void)
 	/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */  /* Led 1 enabled  */
     outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);        /* Led 2 disabled */
 	outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);       /* Led 3 disabled */
-
-
 }
 
 void main(unsigned long bist)
@@ -207,4 +205,3 @@ void main(unsigned long bist)
 	void done_cache_as_ram_main(void);
 	done_cache_as_ram_main();
 }
-

src/mainboard/rca/rm4100/romstage.c

@@ -36,12 +36,11 @@
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
 /**
  * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
  * values have to be set manually, the SO-DIMM socket is located in
@@ -128,4 +127,3 @@ void main(unsigned long bist)
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(64512 * 1024, 65536 * 1024); */
 }
-

src/mainboard/roda/rk886ex/romstage.c

@@ -29,13 +29,10 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <usbdebug.h>
 #include <cpu/x86/bist.h>
-
 #include "northbridge/intel/i945/i945.h"
 #include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
@@ -374,4 +371,3 @@ void main(unsigned long bist)
 	}
 #endif
 }
-

src/mainboard/sunw/ultra40/romstage.c

@@ -9,36 +9,29 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
 #ifdef ENABLE_ONBOARD_SCSI
 static void sio_gpio_setup(void)
 {
@@ -64,12 +57,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 
 //set GPIO to input mode
@@ -82,13 +71,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -183,4 +167,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/supermicro/h8dme/romstage.c

@@ -29,36 +29,26 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -136,20 +126,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -313,6 +296,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
 	post_cache_as_ram();	// bsp swtich stack to ram and copy sysinfo ram now
-
 }
-

src/mainboard/supermicro/h8dmr/romstage.c

@@ -32,36 +32,26 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -81,20 +71,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -30,15 +30,11 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_10xxx_rev.h>
-
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,19 +43,14 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -71,24 +62,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -113,7 +96,6 @@ static void sio_setup(void)
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
 	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-
 }
 
 static const u8 spd_addr[] = {

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -30,15 +30,11 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_10xxx_rev.h>
-
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,19 +43,14 @@
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_SWITCH1 0x70
@@ -74,26 +65,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -116,7 +97,6 @@ static void sio_setup(void)
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
 }
 
 static const u8 spd_addr[] = {
@@ -317,6 +297,4 @@ post_code(0x40);
 // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
  post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
  post_code(0x42);  // Should never see this post code.
-
 }
-

src/mainboard/supermicro/x6dai_g/romstage.c

@@ -64,6 +64,7 @@ static void main(unsigned long bist)
 			skip_romstage();
 		}
 	}
+
 	/* Setup the console */
 	outb(0x87,0x2e);
 	outb(0x87,0x2e);
@@ -115,11 +116,4 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-
-#if 0
-	while(1) {
-		hlt();
-	}
-#endif
 }
-

src/mainboard/supermicro/x6dhe_g/romstage.c

@@ -46,10 +46,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void main(unsigned long bist)
 {
-	/*
-	 *
-	 *
-	 */
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -71,6 +67,7 @@ static void main(unsigned long bist)
 			skip_romstage();
 		}
 	}
+
 	/* Setup the console */
 	outb(0x87,0x2e);
 	outb(0x87,0x2e);
@@ -131,11 +128,4 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-
-#if 0
-	while(1) {
-		hlt();
-	}
-#endif
 }
-

src/mainboard/supermicro/x6dhe_g2/romstage.c

@@ -55,7 +55,6 @@ static void main(unsigned long bist)
 			*/
 		    	.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
 			.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
-
 		}
 	};
 
@@ -66,6 +65,7 @@ static void main(unsigned long bist)
 			skip_romstage();
 		}
 	}
+
 	/* Setup the console */
 	outb(0x87,0x2e);
 	outb(0x87,0x2e);
@@ -126,11 +126,4 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-
-#if 0
-	while(1) {
-		hlt();
-	}
-#endif
 }
-

src/mainboard/supermicro/x6dhr_ig/romstage.c

@@ -45,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void main(unsigned long bist)
 {
-	/*
-	 *
-	 *
-	 */
 	static const struct mem_controller mch[] = {
 		{
 			.node_id = 0,
@@ -70,6 +66,7 @@ static void main(unsigned long bist)
 			skip_romstage();
 		}
 	}
+
 	/* Setup the console */
 	outb(0x87,0x2e);
 	outb(0x87,0x2e);
@@ -131,11 +128,4 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-
-#if 0
-	while(1) {
-		hlt();
-	}
-#endif
 }
-

src/mainboard/supermicro/x6dhr_ig2/romstage.c

@@ -66,6 +66,7 @@ static void main(unsigned long bist)
 			skip_romstage();
 		}
 	}
+
 	/* Setup the console */
 	outb(0x87,0x2e);
 	outb(0x87,0x2e);
@@ -127,11 +128,4 @@ static void main(unsigned long bist)
 #if 0
 	ram_check(0x00000000, 0x02000000);
 #endif
-
-#if 0
-	while(1) {
-		hlt();
-	}
-#endif
 }
-

src/mainboard/technexion/tim5690/romstage.c

@@ -31,24 +31,19 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 
@@ -74,19 +69,12 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "tn_post_code.c"
 #include "speaker.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -203,4 +191,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/technexion/tim8690/romstage.c

@@ -31,24 +31,19 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include <spd.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #include "southbridge/amd/rs690/rs690_early_setup.c"
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 
@@ -74,16 +69,10 @@ static inline int spd_read_byte(u32 device, u32 address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -188,4 +177,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-

src/mainboard/technologic/ts5300/romstage.c

@@ -130,7 +130,6 @@ static void identify_system(void)
 	val=inb(0x19d);
 	if(val==0x5f)
 		identify_ts9500();
-
 }
 
 static void hard_reset(void)
@@ -172,4 +171,3 @@ static void main(unsigned long bist)
 
 	TS5300_LED_OFF;
 }
-

src/mainboard/thomson/ip1000/romstage.c

@@ -37,12 +37,11 @@
 #include "cpu/x86/bist.h"
 #include "spd_table.h"
 #include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
 /**
  * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
  * values have to be set manually, the SO-DIMM socket is located in
@@ -130,4 +129,3 @@ void main(unsigned long bist)
 	/* ram_check(0, 640 * 1024); */
 	/* ram_check(64512 * 1024, 65536 * 1024); */
 }
-

src/mainboard/traverse/geos/romstage.c

@@ -32,7 +32,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 

src/mainboard/tyan/s2735/romstage.c

@@ -1,4 +1,3 @@
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -10,13 +9,10 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
-
 #include "northbridge/intel/e7501/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 

src/mainboard/tyan/s2850/romstage.c

@@ -10,28 +10,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -66,15 +61,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2875/romstage.c

@@ -10,28 +10,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -62,20 +57,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2880/romstage.c

@@ -10,28 +10,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -62,20 +57,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2881/romstage.c

@@ -9,29 +9,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -66,15 +60,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2882/romstage.c

@@ -10,28 +10,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -62,18 +57,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -117,7 +107,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		init_cpus(cpu_init_detectedx);
         }
 
-
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
@@ -147,6 +136,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sdram_initialize(ARRAY_SIZE(cpu), cpu);
 
 	post_cache_as_ram();
-
 }
-

src/mainboard/tyan/s2885/romstage.c

@@ -9,29 +9,23 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -62,22 +56,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -161,6 +146,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
 	post_cache_as_ram();
-
 }
-

src/mainboard/tyan/s2891/romstage.c

@@ -9,9 +9,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
@@ -21,10 +19,8 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -50,19 +46,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)

src/mainboard/tyan/s2892/romstage.c

@@ -6,27 +6,21 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -48,13 +42,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+
 //set GPIO to input mode
 #define CK804_MB_SETUP \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
@@ -63,13 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)

src/mainboard/tyan/s2895/romstage.c

@@ -59,12 +59,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 
 //set GPIO to input mode
@@ -77,11 +73,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)

src/mainboard/tyan/s2912/romstage.c

@@ -32,36 +32,27 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
 #include <lib.h>
 #include <spd.h>
 #include <usbdebug.h>
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -81,9 +72,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 
 #define MCP55_MB_SETUP \
@@ -96,13 +85,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -34,32 +34,24 @@
 #include <usbdebug.h>
 #include <lib.h>
 #include <spd.h>
-
 #include <cpu/amd/model_10xxx_rev.h>
-
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdfam10/debug.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
-
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -71,12 +63,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
-
 #include "cpu/amd/quadcore/quadcore.c"
 
 #define MCP55_MB_SETUP \
@@ -89,14 +78,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 

src/mainboard/tyan/s4880/romstage.c

@@ -9,28 +9,23 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -75,29 +70,22 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
- /* tyan does not want the default */
-#include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
 #include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<4)<<8)
 #define RC3 ((1<<3)<<8)
 
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const struct mem_controller cpu[] = {
@@ -192,4 +180,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_cache_as_ram();
 }
-