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soc/intel/skylake: Enable LAN depending on devicetree configuration 

Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.

Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Felix Singer 2020-07-25 07:50:51 +02:00 committed by Michael Niewöhner
parent 0901d03085
commit 57c8143350
21 changed files with 3 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/51nb/x210/devicetree.cb
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@ -36,7 +36,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "0"

2
src/mainboard/asrock/h110m/devicetree.cb
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@ -125,8 +125,6 @@ chip soc/intel/skylake
.voltage_limit = 1520 \
}"
register "EnableLan" = "0"
# USB
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"

1
src/mainboard/facebook/monolith/devicetree.cb
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@ -47,7 +47,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "0"
register "PmTimerDisabled" = "1"
register "HeciEnabled" = "0"
register "EnableLan" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \

1
src/mainboard/google/eve/devicetree.cb
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@ -36,7 +36,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
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@ -65,7 +65,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/google/glados/devicetree.cb
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@ -38,7 +38,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
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@ -42,7 +42,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "1"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
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@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
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@ -42,7 +42,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

2
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
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@ -50,8 +50,6 @@ chip soc/intel/skylake
# RP17, uses uses CLK SRC 7
register "PcieRpClkSrcNumber[16]" = "7"
register EnableLan = "1"
# USB related
register "SsicPortEnable" = "1"

2
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -140,8 +140,6 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[5]" = "0"
register "PcieRpClkReqNumber[12]" = "1"
register "EnableLan" = "1"
# USB related
register "SsicPortEnable" = "1"

1
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
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@ -34,7 +34,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "0"

1
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -45,7 +45,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
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@ -27,7 +27,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"

5
src/soc/intel/skylake/chip.c
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@ -242,8 +242,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable;
params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchLanEnable = config->EnableLan;
if (config->EnableLan) {
dev = pcidev_path_on_root(PCH_DEVFN_GBE);
params->PchLanEnable = dev ? dev->enabled : 0;
if (params->PchLanEnable) {
params->PchLanLtrEnable = config->EnableLanLtr;
params->PchLanK1OffEnable = config->EnableLanK1Off;
params->PchLanClkReqSupported = config->LanClkReqSupported;

1
src/soc/intel/skylake/chip.h
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@ -136,7 +136,6 @@ struct soc_intel_skylake_config {
u8 CmdTriStateDis;
/* Lan */
u8 EnableLan;
u8 EnableLanLtr;
u8 EnableLanK1Off;
u8 LanClkReqSupported;