added via vt8231
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
2b664dd0a0
commit
57cef6590b
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@ -0,0 +1,2 @@
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config chip.h
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object w83c553f.o
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@ -0,0 +1,14 @@
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#ifndef _SOUTHBRIDGE_VIA_VT8231
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#define _SOUTHBRIDGE_VIA_VT8231
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extern struct chip_control southbridge_via_vt8231_control;
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struct southbridge_via_vt8231_config {
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int enable_usb;
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int enable_native_ide;
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int enable_com_ports;
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int enable_keyboard;
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int enable_nvram;
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};
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#endif /* _SOUTHBRIDGE_VIA_VT8231 */
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@ -0,0 +1,359 @@
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/chip.h>
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#include <console/console.h>
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#include "vt8231.h"
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#include "chip.h"
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void usb_on(int enable)
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{
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unsigned char regval;
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/* Base 8231 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_8231, 0);
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/* USB controller 1 */
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struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_82C586_2, 0);
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/* USB controller 2 */
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struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_82C586_2, \
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dev2);
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/* enable USB1 */
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if(dev2) {
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if (enable) {
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pci_write_config_byte(dev2, 0x3c, 0x05);
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pci_write_config_byte(dev2, 0x04, 0x07);
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} else {
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pci_write_config_byte(dev2, 0x3c, 0x00);
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pci_write_config_byte(dev2, 0x04, 0x00);
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}
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}
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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if (enable)
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regval &= ~(0x10);
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else
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regval |= 0x10;
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pci_write_config_byte(dev0, 0x50, regval);
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}
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/* enable USB2 */
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if(dev3) {
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if (enable) {
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pci_write_config_byte(dev3, 0x3c, 0x05);
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pci_write_config_byte(dev3, 0x04, 0x07);
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} else {
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pci_write_config_byte(dev3, 0x3c, 0x00);
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pci_write_config_byte(dev3, 0x04, 0x00);
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}
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}
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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if (enable)
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regval &= ~(0x20);
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else
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regval |= 0x20;
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pci_write_config_byte(dev0, 0x50, regval);
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}
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}
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void keyboard_on()
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{
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unsigned char regval;
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/* Base 8231 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_8231, 0);
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/* kevinh/Ispiri - update entire function to use
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new pci_write_config_byte */
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if (dev0) {
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pci_read_config_byte(dev0, 0x51, ®val);
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regval |= 0x0f;
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pci_write_config_byte(dev0, 0x51, regval);
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}
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pc_keyboard_init();
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}
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void nvram_on()
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{
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/*
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* the VIA 8231 South has a very different nvram setup than the
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* piix4e ...
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* turn on ProMedia nvram.
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* TO DO: use the PciWriteByte function here.
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*/
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/*
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* kevinh/Ispiri - I don't think this is the correct address/value
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* intel_conf_writeb(0x80008841, 0xFF);
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*/
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}
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/*
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* Enable the ethernet device and turn off stepping (because it is integrated
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* inside the southbridge)
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*/
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void ethernet_fixup()
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{
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struct pci_dev *dev, *edev;
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u8 byte;
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printk_info("Ethernet fixup\n");
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edev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
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if (edev != NULL) {
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printk_debug("Configuring VIA LAN\n");
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/* We don't need stepping - though the device supports it */
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pci_read_config_byte(edev, PCI_COMMAND, &byte);
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byte &= ~PCI_COMMAND_WAIT;
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pci_write_config_byte(edev, PCI_COMMAND, byte);
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} else {
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printk_debug("VIA LAN not found\n");
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}
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}
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void southbridge_fixup()
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{
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unsigned char enables;
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struct pci_dev *dev0;
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struct pci_dev *dev1;
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struct pci_dev *devpwr;
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// to do: use the pcibios_find function here, instead of
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// hard coding the devfn.
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// done - kevinh/Ispiri
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/* Base 8231 controller */
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dev0 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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/* IDE controller */
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dev1 = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, \
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0);
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/* Power management controller */
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devpwr = pci_find_device(PCI_VENDOR_ID_VIA, \
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PCI_DEVICE_ID_VIA_8231_4, 0);
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// enable the internal I/O decode
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enables = pci_read_config_byte(dev0, 0x6C, &enables);
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enables |= 0x80;
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pci_write_config_byte(dev0, 0x6C, enables);
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// Map 4MB of FLASH into the address space
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pci_write_config_byte(dev0, 0x41, 0x7f);
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// Set bit 6 of 0x40, because Award does it (IO recovery time)
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// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
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// interrupts can be properly marked as level triggered.
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enables = pci_read_config_byte(dev0, 0x40, &enables); enables |= 0x44;
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pci_write_config_byte(dev0, 0x40, enables);
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// Set 0x42 to 0xf0 to match Award bios
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enables = pci_read_config_byte(dev0, 0x42, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev0, 0x42, enables);
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// Set bit 3 of 0x4a, to match award (dummy pci request)
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enables = pci_read_config_byte(dev0, 0x4a, &enables);
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enables |= 0x08;
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pci_write_config_byte(dev0, 0x4a, enables);
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// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
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enables = pci_read_config_byte(dev0, 0x4f, &enables);
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enables |= 0x08;
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pci_write_config_byte(dev0, 0x4f, enables);
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// Set 0x58 to 0x03 to match Award
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pci_write_config_byte(dev0, 0x58, 0x03);
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// enable the ethernet/RTC
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if(dev0) {
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pci_read_config_byte(dev0, 0x51, &enables);
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enables |= 0x18;
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pci_write_config_byte(dev0, 0x51, enables);
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}
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// enable com1 and com2.
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if (conf->enable_com_ports) {
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enables = pci_read_config_byte(dev0, 0x6e, &enables);
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/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
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* is enable com port a as com1 kevinh/Ispiri - Old code
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* thought 0x01 would make it com1, that was wrong /*
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* enables = 0x80 | 0x10 | 0x8 ; pci_write_config_byte(dev0,
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* 0x6e, enables); // note: this is also a redo of some port
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* of assembly, but we want everything up.
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*/
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/* set com1 to 115 kbaud not clear how to do this yet.
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* forget it; done in assembly.
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*/
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#endif
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// enable IDE, since Linux won't do it.
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// First do some more things to devfn (17,0)
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// note: this should already be cleared, according to the book.
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pci_read_config_byte(dev0, 0x50, &enables);
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printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
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enables &= ~8; // need manifest constant here!
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printk_debug("set IDE reg. 50 to 0x%x\n", enables);
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pci_write_config_byte(dev0, 0x50, enables);
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// set default interrupt values (IDE)
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pci_read_config_byte(dev0, 0x4c, &enables);
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printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
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// clear out whatever was there.
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enables &= ~0xf;
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enables |= 4;
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printk_debug("setting reg. 4c to 0x%x\n", enables);
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pci_write_config_byte(dev0, 0x4c, enables);
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// set up the serial port interrupts.
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// com2 to 3, com1 to 4
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pci_write_config_byte(dev0, 0x46, 0x04);
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pci_write_config_byte(dev0, 0x47, 0x03);
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//
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// Power management setup
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//
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// Set ACPI base address to IO 0x4000
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pci_write_config_dword(devpwr, 0x48, 0x4001);
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// Enable ACPI access (and setup like award)
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pci_write_config_byte(devpwr, 0x41, 0x84);
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// Set hardware monitor base address to IO 0x6000
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pci_write_config_dword(devpwr, 0x70, 0x6001);
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// Enable hardware monitor (and setup like award)
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pci_write_config_byte(devpwr, 0x74, 0x01);
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// set IO base address to 0x5000
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pci_write_config_dword(devpwr, 0x90, 0x5001);
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// Enable SMBus
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pci_write_config_byte(devpwr, 0xd2, 0x01);
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//
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// IDE setup
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//
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if (conf->enable_native_ide) {
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// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
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// interrupts. Using PCI ints confuses linux for some reason.
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pci_read_config_byte(dev1, 0x42, &enables);
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printk_debug("enables in reg 0x42 0x%x\n", enables);
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enables &= ~0xc0; // compatability mode
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pci_write_config_byte(dev1, 0x42, enables);
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pci_read_config_byte(dev1, 0x42, &enables);
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printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
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}
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pci_read_config_byte(dev1, 0x40, &enables);
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printk_debug("enables in reg 0x40 0x%x\n", enables);
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enables |= 3;
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pci_write_config_byte(dev1, 0x40, enables);
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pci_read_config_byte(dev1, 0x40, &enables);
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printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
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// Enable prefetch buffers
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pci_read_config_byte(dev1, 0x41, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev1, 0x41, enables);
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// Lower thresholds (cause award does it)
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pci_read_config_byte(dev1, 0x43, &enables);
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enables &= ~0x0f;
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enables |= 0x05;
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pci_write_config_byte(dev1, 0x43, enables);
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// PIO read prefetch counter (cause award does it)
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pci_write_config_byte(dev1, 0x44, 0x18);
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// Use memory read multiple
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pci_write_config_byte(dev1, 0x45, 0x1c);
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// address decoding.
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// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
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// kevinh@ispiri.com - the standard linux drivers seem ass slow when
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// used in native mode - I've changed back to classic
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pci_read_config_byte(dev1, 0x9, &enables);
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printk_debug("enables in reg 0x9 0x%x\n", enables);
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// by the book, set the low-order nibble to 0xa.
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if (conf->enable_native_ide) {
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enables &= ~0xf;
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// cf/cg silicon needs an 'f' here.
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enables |= 0xf;
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} else {
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enables &= ~0x5;
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}
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pci_write_config_byte(dev1, 0x9, enables);
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pci_read_config_byte(dev1, 0x9, &enables);
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printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
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// standard bios sets master bit.
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 0x%x\n", enables);
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enables |= 7;
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// No need for stepping - kevinh@ispiri.com
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enables &= ~0x80;
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pci_write_config_byte(dev1, 0x4, enables);
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
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if (! conf->enable_native_ide) {
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// Use compatability mode - per award bios
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pci_write_config_dword(dev1, 0x10, 0x0);
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pci_write_config_dword(dev1, 0x14, 0x0);
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pci_write_config_dword(dev1, 0x18, 0x0);
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pci_write_config_dword(dev1, 0x1c, 0x0);
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// Force interrupts to use compat mode - just like Award bios
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pci_write_config_byte(dev1, 0x3d, 00);
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pci_write_config_byte(dev1, 0x3c, 0xff);
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}
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ethernet_fixup();
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// Start the rtc
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rtc_init(0);
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}
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static void
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southbridge_init(struct chip *chip, enum chip_pass pass)
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{
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struct southbridge_via_vt8231_config *conf =
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(struct southbridge_via_vt8231_config *)chip->chip_info;
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switch (pass) {
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|
case CONF_PASS_POST_PCI:
|
||||||
|
vt8231_init(conf);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
/* nothing yet */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_control southbridge_via_vt8231_control = {
|
||||||
|
enable: southbridge_init,
|
||||||
|
name: "VIA vt8231"
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,195 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2000
|
||||||
|
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* winbond access routines and defines*/
|
||||||
|
|
||||||
|
/* from the winbond data sheet -
|
||||||
|
The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
|
||||||
|
Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*ISA bridge configuration space*/
|
||||||
|
|
||||||
|
#define W83C553F_VID 0x10AD
|
||||||
|
#define W83C553F_DID 0x0565
|
||||||
|
#define W83C553F_IDE 0x0105
|
||||||
|
|
||||||
|
/* Function 0 registers */
|
||||||
|
#define W83C553F_PCICONTR 0x40 /*pci control reg*/
|
||||||
|
#define W83C553F_SGBAR 0x41 /*scatter/gather base address reg*/
|
||||||
|
#define W83C553F_LBCR 0x42 /*Line Buffer Control reg*/
|
||||||
|
#define W83C553F_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
|
||||||
|
#define W83C553F_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
|
||||||
|
#define W83C553F_BTBAR 0x46 /*BIOS Timer Base Address Register*/
|
||||||
|
#define W83C553F_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
|
||||||
|
#define W83C553F_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
|
||||||
|
#define W83C553F_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
|
||||||
|
#define W83C553F_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
|
||||||
|
#define W83C553F_CDR 0x4c /*Clock Divisor Register*/
|
||||||
|
#define W83C553F_CSCR 0x4d /*Chip Select Control Register*/
|
||||||
|
#define W83C553F_ATSCR 0x4e /*AT System Control register*/
|
||||||
|
#define W83C553F_ATBCR 0x4f /*AT Bus ControL Register*/
|
||||||
|
#define W83C553F_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
|
||||||
|
#define W83C553F_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
|
||||||
|
#define W83C553F_ABEER 0x62 /*Additional Break Event Enable Register*/
|
||||||
|
#define W83C553F_DMABEER 0x63 /*DMA Break Event Enable Register*/
|
||||||
|
|
||||||
|
/* Function 1 registers */
|
||||||
|
#define W83C553F_PIR 0x09 /*Programming Interface Register*/
|
||||||
|
#define W83C553F_IDECSR 0x40 /*IDE Control/Status Register*/
|
||||||
|
|
||||||
|
/* register bit definitions */
|
||||||
|
#define W83C553F_IPADCR_MBE512 0x1
|
||||||
|
#define W83C553F_IPADCR_MBE640 0x2
|
||||||
|
#define W83C553F_IPADCR_IPATOM4 0x10
|
||||||
|
#define W83C553F_IPADCR_IPATOM5 0x20
|
||||||
|
#define W83C553F_IPADCR_IPATOM6 0x40
|
||||||
|
#define W83C553F_IPADCR_IPATOM7 0x80
|
||||||
|
|
||||||
|
#define W83C553F_CSCR_UBIOSCSE 0x10
|
||||||
|
#define W83C553F_CSCR_BIOSWP 0x20
|
||||||
|
|
||||||
|
#define W83C553F_IDECSR_P0EN 0x01
|
||||||
|
#define W83C553F_IDECSR_P0F16 0x02
|
||||||
|
#define W83C553F_IDECSR_P1EN 0x10
|
||||||
|
#define W83C553F_IDECSR_P1F16 0x20
|
||||||
|
#define W83C553F_IDECSR_LEGIRQ 0x800
|
||||||
|
|
||||||
|
#define W83C553F_ATSCR_ISARE 0x40
|
||||||
|
#define W83C553F_ATSCR_FERRE 0x10
|
||||||
|
#define W83C553F_ATSCR_P92E 0x04
|
||||||
|
#define W83C553F_ATSCR_KRCEE 0x02
|
||||||
|
#define W83C553F_ATSCR_KGA20EE 0x01
|
||||||
|
|
||||||
|
#define W83C553F_PIR_BM 0x80
|
||||||
|
#define W83C553F_PIR_P1PROG 0x08
|
||||||
|
#define W83C553F_PIR_P1NL 0x04
|
||||||
|
#define W83C553F_PIR_P0PROG 0x02
|
||||||
|
#define W83C553F_PIR_P0NL 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Interrupt controller
|
||||||
|
*/
|
||||||
|
#define W83C553F_PIC1_ICW1 CONFIG_ISA_IO + 0x20
|
||||||
|
#define W83C553F_PIC1_ICW2 CONFIG_ISA_IO + 0x21
|
||||||
|
#define W83C553F_PIC1_ICW3 CONFIG_ISA_IO + 0x21
|
||||||
|
#define W83C553F_PIC1_ICW4 CONFIG_ISA_IO + 0x21
|
||||||
|
#define W83C553F_PIC1_OCW1 CONFIG_ISA_IO + 0x21
|
||||||
|
#define W83C553F_PIC1_OCW2 CONFIG_ISA_IO + 0x20
|
||||||
|
#define W83C553F_PIC1_OCW3 CONFIG_ISA_IO + 0x20
|
||||||
|
#define W83C553F_PIC1_ELC CONFIG_ISA_IO + 0x4D0
|
||||||
|
#define W83C553F_PIC2_ICW1 CONFIG_ISA_IO + 0xA0
|
||||||
|
#define W83C553F_PIC2_ICW2 CONFIG_ISA_IO + 0xA1
|
||||||
|
#define W83C553F_PIC2_ICW3 CONFIG_ISA_IO + 0xA1
|
||||||
|
#define W83C553F_PIC2_ICW4 CONFIG_ISA_IO + 0xA1
|
||||||
|
#define W83C553F_PIC2_OCW1 CONFIG_ISA_IO + 0xA1
|
||||||
|
#define W83C553F_PIC2_OCW2 CONFIG_ISA_IO + 0xA0
|
||||||
|
#define W83C553F_PIC2_OCW3 CONFIG_ISA_IO + 0xA0
|
||||||
|
#define W83C553F_PIC2_ELC CONFIG_ISA_IO + 0x4D1
|
||||||
|
|
||||||
|
#define W83C553F_TMR1_CMOD CONFIG_ISA_IO + 0x43
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DMA controller
|
||||||
|
*/
|
||||||
|
#define W83C553F_DMA1 CONFIG_ISA_IO + 0x000 /* channel 0 - 3 */
|
||||||
|
#define W83C553F_DMA2 CONFIG_ISA_IO + 0x0C0 /* channel 4 - 7 */
|
||||||
|
|
||||||
|
/* command/status register bit definitions */
|
||||||
|
|
||||||
|
#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
|
||||||
|
#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
|
||||||
|
#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
|
||||||
|
#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
|
||||||
|
|
||||||
|
#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
|
||||||
|
#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
|
||||||
|
#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
|
||||||
|
#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
|
||||||
|
|
||||||
|
#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
|
||||||
|
#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
|
||||||
|
#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
|
||||||
|
#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
|
||||||
|
|
||||||
|
/* mode register bit definitions */
|
||||||
|
|
||||||
|
#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
|
||||||
|
#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
|
||||||
|
#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
|
||||||
|
#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
|
||||||
|
#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
|
||||||
|
#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
|
||||||
|
#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
|
||||||
|
#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
|
||||||
|
#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
|
||||||
|
#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
|
||||||
|
#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||||
|
#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||||
|
#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||||
|
#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||||
|
|
||||||
|
/* request register bit definitions */
|
||||||
|
|
||||||
|
#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
|
||||||
|
#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||||
|
#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||||
|
#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||||
|
#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||||
|
|
||||||
|
/* write single mask bit register bit definitions */
|
||||||
|
|
||||||
|
#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
|
||||||
|
#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
|
||||||
|
#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
|
||||||
|
#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
|
||||||
|
#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
|
||||||
|
|
||||||
|
/* read/write all mask bits register bit definitions */
|
||||||
|
|
||||||
|
#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
|
||||||
|
#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
|
||||||
|
#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
|
||||||
|
#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
|
||||||
|
|
||||||
|
/* typedefs */
|
||||||
|
|
||||||
|
#define W83C553F_DMA1_CS 0x8
|
||||||
|
#define W83C553F_DMA1_WR 0x9
|
||||||
|
#define W83C553F_DMA1_WSMB 0xA
|
||||||
|
#define W83C553F_DMA1_WM 0xB
|
||||||
|
#define W83C553F_DMA1_CBP 0xC
|
||||||
|
#define W83C553F_DMA1_MC 0xD
|
||||||
|
#define W83C553F_DMA1_CM 0xE
|
||||||
|
#define W83C553F_DMA1_RWAMB 0xF
|
||||||
|
|
||||||
|
#define W83C553F_DMA2_CS 0xD0
|
||||||
|
#define W83C553F_DMA2_WR 0xD2
|
||||||
|
#define W83C553F_DMA2_WSMB 0xD4
|
||||||
|
#define W83C553F_DMA2_WM 0xD6
|
||||||
|
#define W83C553F_DMA2_CBP 0xD8
|
||||||
|
#define W83C553F_DMA2_MC 0xDA
|
||||||
|
#define W83C553F_DMA2_CM 0xDC
|
||||||
|
#define W83C553F_DMA2_RWAMB 0xDE
|
||||||
|
|
||||||
|
void initialise_w83c553f(void);
|
||||||
Loading…
Reference in New Issue