Early work on IWill DK8S2 motherboard.
Tweaking in progress. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
David W. Hendricks
parent
36a74b0c18
commit
58133c29fe
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@ -171,8 +171,8 @@ makerule ./failover.inc
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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depends "$(MAINBOARD)/auto.c option_table.h"
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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@ -264,21 +264,50 @@ northbridge amd/amdk8 "mc0"
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 off
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superio winbond/w83627thf link 1
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pnp 2e.0
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pnp 2e.1
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pnp 2e.2
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pnp 2e.3
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pnp 2e.4
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pnp 2e.5
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pnp 2e.6
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pnp 2e.7
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pnp 2e.8
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pnp 2e.9
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pnp 2e.a
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register "com1" = "{1, 0, 0x3f8, 4}"
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register "lpt" = "{1}"
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end
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superio winbond/w83627hf link 1
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pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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# pnp 2e.1 off # Parallel Port
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# io 0x60 = 0x378
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# irq 0x70 = 7
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pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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pnp 2e.6 off # CIR
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pnp 2e.7 off # GAME_MIDI_GIPO1
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pnp 2e.8 off # GPIO2
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pnp 2e.9 off # GPIO3
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pnp 2e.a off # ACPI
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pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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# superio winbond/w83627hf link 1
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# pnp 2e.0
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# pnp 2e.1
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# pnp 2e.2
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# pnp 2e.3
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# pnp 2e.4
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# pnp 2e.5
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# pnp 2e.6
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# pnp 2e.7
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# pnp 2e.8
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# pnp 2e.9
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# pnp 2e.a
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# register "com1" = "{1, 0, 0x3f8, 4}"
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# register "lpt" = "{1}"
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# end
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end
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end
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@ -1,14 +1,17 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <cpu/p6/apic.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/smp/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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@ -17,8 +20,26 @@
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#define SIO_BASE 0x2e
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void hard_reset(void)
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{
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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static void memreset_setup(void)
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{
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@ -102,6 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#if 0
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static void enable_lapic(void)
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{
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@ -154,6 +176,7 @@ static void pc87360_enable_serial(void)
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pnp_set_enable(SIO_BASE, 1);
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pnp_set_iobase0(SIO_BASE, 0x3f8);
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}
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#endif
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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@ -188,22 +211,31 @@ static void main(void)
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},
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#endif
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};
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int needs_reset;
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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enable_lapic();
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init_timer();
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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pc87360_enable_serial();
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain(0);
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distinguish_cpu_resets(0);
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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#if 0
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print_pci_devices();
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#endif
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@ -1,5 +1,5 @@
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extern struct chip_control mainboard_arima_hdama_control;
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extern struct chip_control mainboard_Iwill_DK8S2_control;
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struct mainboard_arima_hdama_config {
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struct mainboard_Iwill_DK8S2_config {
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int nothing;
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};
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@ -29,6 +29,9 @@ entries
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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@ -36,6 +39,7 @@ entries
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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444 1 e 1 nmi
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1008 16 h 0 check_sum
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enumerations
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@ -14,7 +14,7 @@ static void main(void)
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{
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain(0);
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enumerate_ht_chain();
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/* Setup the 8111 */
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amd8111_enable_rom();
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@ -1,52 +1,37 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
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*
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* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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#include <device/pci.h>
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#define IRQ_ROUTER_BUS 1
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#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
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#define IRQ_ROUTER_VENDOR 0x1022
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#define IRQ_ROUTER_DEVICE 0x746b
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#define AVAILABLE_IRQS 0xdef8
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#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
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{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
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{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
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/* Each IRQ_SLOT entry consists of:
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* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
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* devices on the bus */
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IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
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IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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IRQ_ROUTER_VENDOR, /* Vendor */
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IRQ_ROUTER_DEVICE, /* Device */
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0x00, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x00, /* u8 checksum , mod 256 checksum must give
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* zero, will be corrected later
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*/
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*12, /* there can be total 12 devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
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/* PCI Slot 1-6 */
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IRQ_SLOT (1, 3,1,0, 2,3,4,1 ),
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IRQ_SLOT (2, 3,2,0, 3,4,1,2 ),
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IRQ_SLOT (3, 2,1,0, 2,3,4,1 ),
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IRQ_SLOT (4, 2,2,0, 3,4,1,2 ),
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IRQ_SLOT (5, 4,5,0, 2,3,4,1 ),
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IRQ_SLOT (6, 4,4,0, 1,2,3,4 ),
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/* Onboard NICs */
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IRQ_SLOT (0, 2,3,0, 4,0,0,0 ),
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IRQ_SLOT (0, 2,4,0, 4,0,0,0 ),
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/* Let Linux know about bus 1 */
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IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
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{0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
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{0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
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{0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
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{0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0},
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{0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0},
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{0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0},
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{0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0},
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{0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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}
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};
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@ -34,8 +34,8 @@ static void enumerate(struct chip *chip)
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child->bus = &dev_root.link[0];
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}
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}
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struct chip_control mainboard_arima_hdama_control = {
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struct chip_control mainboard_Iwill_DK8S2_control = {
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.enumerate = enumerate,
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.name = "Arima HDAMA mainboard ",
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.name = "Iwill DK8S2 mainboard ",
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};
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