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soc/intel: Fix ugly preprocessor macro 

Macro hides that dev_find_slot() takes two arguments.

Change-Id: I639af31b9d4a2d702dfd2baebddbb8352e8bf9b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Kyösti Mälkki 2018-12-29 10:28:08 +02:00
parent 3521e260e3
commit 581383aaed
4 changed files with 4 additions and 4 deletions
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2
src/soc/intel/fsp_baytrail/acpi.c
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@ -173,7 +173,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t;
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{ {
acpi_header_t *header = &(fadt->header); acpi_header_t *header = &(fadt->header);
struct device *lpcdev = dev_find_slot(FADT_SOC_LPC_DEV); struct device *lpcdev = dev_find_slot(0, FADT_SOC_LPC_DEVFN);
u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
config_t *config = lpcdev->chip_info; config_t *config = lpcdev->chip_info;

2
src/soc/intel/fsp_baytrail/include/soc/lpc.h
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@ -17,7 +17,7 @@
#ifndef _BAYTRAIL_LPC_H_ #ifndef _BAYTRAIL_LPC_H_
#define _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_
#define FADT_SOC_LPC_DEV 0, PCI_DEVFN(0x1f,0) #define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0)
/* PCI config registers in LPC bridge. */ /* PCI config registers in LPC bridge. */
#define REVID 0x08 #define REVID 0x08

2
src/southbridge/intel/fsp_rangeley/acpi.c
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@ -34,7 +34,7 @@ typedef struct southbridge_intel_fsp_rangeley_config config_t;
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{ {
acpi_header_t *header = &(fadt->header); acpi_header_t *header = &(fadt->header);
struct device *lpcdev = dev_find_slot(SOC_LPC_DEVFN); struct device *lpcdev = dev_find_slot(0, SOC_LPC_DEVFN);
u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
config_t *config = lpcdev->chip_info; config_t *config = lpcdev->chip_info;

2
src/southbridge/intel/fsp_rangeley/soc.h
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@ -92,7 +92,7 @@ void rangeley_sb_early_initialization(void);
/* PCI Configuration Space (D31:F0): LPC */ /* PCI Configuration Space (D31:F0): LPC */
#define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0) #define SOC_LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SOC_LPC_DEVFN 0, PCI_DEVFN(0x1f,0) #define SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0)
/* Southbridge IO BARs */ /* Southbridge IO BARs */