adapt config files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
800a55bb5c
commit
584e078231
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@ -1,123 +1,3 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE=524288
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=4
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default HARD_RESET_FUNCTION=0
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=9
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=4
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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default MAINBOARD_PART_NUMBER="QUARTET"
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default MAINBOARD_VENDOR="AMD"
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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##
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## Compute the location and size of where this firmware image
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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@ -136,7 +16,6 @@ end
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##
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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##
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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## Compute where this copy of linuxBIOS will start in the boot rom
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@ -153,12 +32,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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default XIP_ROM_SIZE=65536
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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arch i386 end
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#cpu k8 end
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##
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##
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## Build the objects we have code for in this directory.
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## Build the objects we have code for in this directory.
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@ -193,21 +67,20 @@ end
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##
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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mainboardinit cpu/i386/bist32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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ldscript /cpu/i386/entry32.lds
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##
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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##
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if USE_FALLBACK_IMAGE
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/i386/reset16.lds
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ldscript /cpu/x86/16bit/reset16.lds
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else
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else
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mainboardinit cpu/i386/reset32.inc
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/i386/reset32.lds
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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### Should this be in the northbridge code?
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### Should this be in the northbridge code?
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@ -219,11 +92,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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ldscript /arch/i386/lib/id.lds
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/k8/earlymtrr.inc
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###
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###
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### This is the early phase of linuxBIOS startup
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### Things are delicate and we test to see if we should
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##
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##
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## Setup RAM
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## Setup RAM
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##
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##
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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##
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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@ -255,9 +126,9 @@ chip northbridge/amd/amdk8 # mc0
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device pci_domain 0 on
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device pci_domain 0 on
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.0
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device pci 18.0 on
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chip southbridge amd/amd8111
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chip southbridge/amd/amd8111
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device pci 0:0.0 on
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device pci 0.0 on
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device pci 0.0 on end
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.1 on end
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device pci 0.2 on end
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device pci 0.2 on end
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@ -300,8 +171,8 @@ chip northbridge/amd/amdk8 # mc0
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device pci 1.3 on end
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device pci 1.3 on end
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device pci 1.5 on end
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device pci 1.5 on end
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device pci 1.6 on end
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device pci 1.6 on end
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end
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end # 8111
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end
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.3 on end
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@ -309,13 +180,13 @@ chip northbridge/amd/amdk8 # mc0
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chip northbridge/amd/amdk8 # mc1
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chip northbridge/amd/amdk8 # mc1
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device pci 19.0 on end
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device pci 19.0 on end
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device pci 19.0 on
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device pci 19.0 on
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chip southbridge amd/amd8131 # amd8131_0
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chip southbridge/amd/amd8131 # amd8131_0
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device pci 0.0 on end
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.0 on end
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device pci 1.1 on end
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device pci 1.1 on end
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end
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end
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chip southbridge amd/amd8131 # amd8131_1
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chip southbridge/amd/amd8131 # amd8131_1
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device pci 0.0 on end
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 0.1 on end
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device pci 1.0 on end
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device pci 1.0 on end
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@ -362,10 +233,3 @@ chip northbridge/amd/amdk8 # mc0
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end
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end
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end
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end
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##
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## Include the old serial code for those few places that still need it.
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit cpu/i386/bist32_fail.inc
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@ -0,0 +1,210 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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uses CC
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uses HOSTCC
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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###
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### Build options
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###
|
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##
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## ROM_SIZE is the size of boot ROM that this board will use.
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||||||
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##
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default ROM_SIZE=524288
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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default FALLBACK_SIZE=131072
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##
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## Build code for the fallback boot
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||||||
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##
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||||||
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default HAVE_FALLBACK_BOOT=1
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|
||||||
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##
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||||||
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## Build code to reset the motherboard from linuxBIOS
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||||||
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##
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||||||
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default HAVE_HARD_RESET=1
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||||||
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|
||||||
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##
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## Funky hard reset implementation
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||||||
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##
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||||||
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default HARD_RESET_BUS=1
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default HARD_RESET_DEVICE=4
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||||||
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default HARD_RESET_FUNCTION=0
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||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a programmable irq routing table
|
||||||
|
##
|
||||||
|
default HAVE_PIRQ_TABLE=1
|
||||||
|
default IRQ_SLOT_COUNT=9
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export an x86 MP table
|
||||||
|
## Useful for specifying IRQ routing values
|
||||||
|
##
|
||||||
|
default HAVE_MP_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a CMOS option table
|
||||||
|
##
|
||||||
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default HAVE_OPTION_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||||
|
##
|
||||||
|
default LB_CKS_RANGE_START=49
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||||||
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default LB_CKS_RANGE_END=122
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||||||
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default LB_CKS_LOC=123
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||||||
|
|
||||||
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##
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||||||
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## Build code for SMP support
|
||||||
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## Only worry about 2 micro processors
|
||||||
|
##
|
||||||
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default CONFIG_SMP=1
|
||||||
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default CONFIG_MAX_CPUS=4
|
||||||
|
|
||||||
|
##
|
||||||
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## Build code to setup a generic IOAPIC
|
||||||
|
##
|
||||||
|
default CONFIG_IOAPIC=1
|
||||||
|
|
||||||
|
##
|
||||||
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## Clean up the motherboard id strings
|
||||||
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##
|
||||||
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default MAINBOARD_PART_NUMBER="QUARTET"
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||||||
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default MAINBOARD_VENDOR="AMD"
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||||||
|
|
||||||
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###
|
||||||
|
### LinuxBIOS layout values
|
||||||
|
###
|
||||||
|
|
||||||
|
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||||
|
default ROM_IMAGE_SIZE = 65536
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 8K stack
|
||||||
|
##
|
||||||
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default STACK_SIZE=0x2000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 16K heap
|
||||||
|
##
|
||||||
|
default HEAP_SIZE=0x4000
|
||||||
|
|
||||||
|
##
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||||||
|
## Only use the option table in a normal image
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||||||
|
##
|
||||||
|
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||||
|
|
||||||
|
##
|
||||||
|
## LinuxBIOS C code runs at this location in RAM
|
||||||
|
##
|
||||||
|
default _RAMBASE=0x00004000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Load the payload from the ROM
|
||||||
|
##
|
||||||
|
default CONFIG_ROM_STREAM = 1
|
||||||
|
|
||||||
|
###
|
||||||
|
### Defaults of options that you may want to override in the target config file
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## The default compiler
|
||||||
|
##
|
||||||
|
default CC="gcc -m32"
|
||||||
|
default HOSTCC="gcc"
|
||||||
|
|
||||||
|
##
|
||||||
|
## The Serial Console
|
||||||
|
##
|
||||||
|
|
||||||
|
# To Enable the Serial Console
|
||||||
|
default CONFIG_CONSOLE_SERIAL8250=1
|
||||||
|
|
||||||
|
## Select the serial console baud rate
|
||||||
|
default TTYS0_BAUD=115200
|
||||||
|
#default TTYS0_BAUD=57600
|
||||||
|
#default TTYS0_BAUD=38400
|
||||||
|
#default TTYS0_BAUD=19200
|
||||||
|
#default TTYS0_BAUD=9600
|
||||||
|
#default TTYS0_BAUD=4800
|
||||||
|
#default TTYS0_BAUD=2400
|
||||||
|
#default TTYS0_BAUD=1200
|
||||||
|
|
||||||
|
# Select the serial console base port
|
||||||
|
default TTYS0_BASE=0x3f8
|
||||||
|
|
||||||
|
# Select the serial protocol
|
||||||
|
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||||
|
default TTYS0_LCS=0x3
|
||||||
|
|
||||||
|
##
|
||||||
|
### Select the linuxBIOS loglevel
|
||||||
|
##
|
||||||
|
## EMERG 1 system is unusable
|
||||||
|
## ALERT 2 action must be taken immediately
|
||||||
|
## CRIT 3 critical conditions
|
||||||
|
## ERR 4 error conditions
|
||||||
|
## WARNING 5 warning conditions
|
||||||
|
## NOTICE 6 normal but significant condition
|
||||||
|
## INFO 7 informational
|
||||||
|
## DEBUG 8 debug-level messages
|
||||||
|
## SPEW 9 Way too many details
|
||||||
|
|
||||||
|
## Request this level of debugging output
|
||||||
|
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||||
|
## At a maximum only compile in this level of debugging
|
||||||
|
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||||
|
|
||||||
|
##
|
||||||
|
## Select power on after power fail setting
|
||||||
|
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||||
|
|
||||||
|
### End Options.lb
|
||||||
|
end
|
||||||
|
|
@ -1,123 +1,3 @@
|
||||||
uses HAVE_MP_TABLE
|
|
||||||
uses HAVE_PIRQ_TABLE
|
|
||||||
uses USE_FALLBACK_IMAGE
|
|
||||||
uses HAVE_FALLBACK_BOOT
|
|
||||||
uses HAVE_HARD_RESET
|
|
||||||
uses HARD_RESET_BUS
|
|
||||||
uses HARD_RESET_DEVICE
|
|
||||||
uses HARD_RESET_FUNCTION
|
|
||||||
uses IRQ_SLOT_COUNT
|
|
||||||
uses HAVE_OPTION_TABLE
|
|
||||||
uses CONFIG_MAX_CPUS
|
|
||||||
uses CONFIG_IOAPIC
|
|
||||||
uses CONFIG_SMP
|
|
||||||
uses FALLBACK_SIZE
|
|
||||||
uses ROM_SIZE
|
|
||||||
uses ROM_SECTION_SIZE
|
|
||||||
uses ROM_IMAGE_SIZE
|
|
||||||
uses ROM_SECTION_SIZE
|
|
||||||
uses ROM_SECTION_OFFSET
|
|
||||||
uses CONFIG_ROM_STREAM
|
|
||||||
uses CONFIG_ROM_STREAM_START
|
|
||||||
uses PAYLOAD_SIZE
|
|
||||||
uses _ROMBASE
|
|
||||||
uses XIP_ROM_SIZE
|
|
||||||
uses XIP_ROM_BASE
|
|
||||||
uses STACK_SIZE
|
|
||||||
uses HEAP_SIZE
|
|
||||||
uses USE_OPTION_TABLE
|
|
||||||
uses LB_CKS_RANGE_START
|
|
||||||
uses LB_CKS_RANGE_END
|
|
||||||
uses LB_CKS_LOC
|
|
||||||
uses MAINBOARD_PART_NUMBER
|
|
||||||
uses MAINBOARD_VENDOR
|
|
||||||
|
|
||||||
|
|
||||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
|
||||||
default ROM_SIZE=524288
|
|
||||||
|
|
||||||
###
|
|
||||||
### Build options
|
|
||||||
###
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code for the fallback boot
|
|
||||||
##
|
|
||||||
default HAVE_FALLBACK_BOOT=1
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code to reset the motherboard from linuxBIOS
|
|
||||||
##
|
|
||||||
default HAVE_HARD_RESET=1
|
|
||||||
|
|
||||||
default HARD_RESET_BUS=1
|
|
||||||
default HARD_RESET_DEVICE=4
|
|
||||||
default HARD_RESET_FUNCTION=0
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code to export a programmable irq routing table
|
|
||||||
##
|
|
||||||
default HAVE_PIRQ_TABLE=1
|
|
||||||
default IRQ_SLOT_COUNT=12
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code to export an x86 MP table
|
|
||||||
## Useful for specifying IRQ routing values
|
|
||||||
##
|
|
||||||
default HAVE_MP_TABLE=1
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code to export a CMOS option table
|
|
||||||
##
|
|
||||||
default HAVE_OPTION_TABLE=1
|
|
||||||
|
|
||||||
##
|
|
||||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
|
||||||
##
|
|
||||||
default LB_CKS_RANGE_START=49
|
|
||||||
default LB_CKS_RANGE_END=122
|
|
||||||
default LB_CKS_LOC=123
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code for SMP support
|
|
||||||
## Only worry about 2 micro processors
|
|
||||||
##
|
|
||||||
default CONFIG_SMP=1
|
|
||||||
default CONFIG_MAX_CPUS=2
|
|
||||||
|
|
||||||
##
|
|
||||||
## Build code to setup a generic IOAPIC
|
|
||||||
##
|
|
||||||
default CONFIG_IOAPIC=1
|
|
||||||
|
|
||||||
##
|
|
||||||
## Clean up the motherboard id strings
|
|
||||||
##
|
|
||||||
default MAINBOARD_PART_NUMBER="HDAMA"
|
|
||||||
default MAINBOARD_VENDOR="ARIMA"
|
|
||||||
|
|
||||||
###
|
|
||||||
### LinuxBIOS layout values
|
|
||||||
###
|
|
||||||
|
|
||||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
|
||||||
default ROM_IMAGE_SIZE = 65536
|
|
||||||
|
|
||||||
##
|
|
||||||
## Use a small 8K stack
|
|
||||||
##
|
|
||||||
default STACK_SIZE=0x2000
|
|
||||||
|
|
||||||
##
|
|
||||||
## Use a small 16K heap
|
|
||||||
##
|
|
||||||
default HEAP_SIZE=0x8000
|
|
||||||
|
|
||||||
##
|
|
||||||
## Only use the option table in a normal image
|
|
||||||
##
|
|
||||||
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
|
||||||
|
|
||||||
##
|
##
|
||||||
## Compute the location and size of where this firmware image
|
## Compute the location and size of where this firmware image
|
||||||
## (linuxBIOS plus bootloader) will live in the boot rom chip.
|
## (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||||
|
|
@ -136,7 +16,6 @@ end
|
||||||
##
|
##
|
||||||
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||||
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||||
default CONFIG_ROM_STREAM = 1
|
|
||||||
|
|
||||||
##
|
##
|
||||||
## Compute where this copy of linuxBIOS will start in the boot rom
|
## Compute where this copy of linuxBIOS will start in the boot rom
|
||||||
|
|
@ -153,12 +32,7 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
|
||||||
default XIP_ROM_SIZE=65536
|
default XIP_ROM_SIZE=65536
|
||||||
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
|
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
|
||||||
|
|
||||||
##
|
|
||||||
## Set all of the defaults for an x86 architecture
|
|
||||||
##
|
|
||||||
|
|
||||||
arch i386 end
|
arch i386 end
|
||||||
#cpu k8 end
|
|
||||||
|
|
||||||
##
|
##
|
||||||
## Build the objects we have code for in this directory.
|
## Build the objects we have code for in this directory.
|
||||||
|
|
@ -193,21 +67,20 @@ end
|
||||||
##
|
##
|
||||||
## Build our 16 bit and 32 bit linuxBIOS entry code
|
## Build our 16 bit and 32 bit linuxBIOS entry code
|
||||||
##
|
##
|
||||||
mainboardinit cpu/i386/entry16.inc
|
mainboardinit cpu/x86/16bit/entry16.inc
|
||||||
mainboardinit cpu/i386/entry32.inc
|
mainboardinit cpu/x86/32bit/entry32.inc
|
||||||
mainboardinit cpu/i386/bist32.inc
|
ldscript /cpu/x86/16bit/entry16.lds
|
||||||
ldscript /cpu/i386/entry16.lds
|
ldscript /cpu/x86/32bit/entry32.lds
|
||||||
ldscript /cpu/i386/entry32.lds
|
|
||||||
|
|
||||||
##
|
##
|
||||||
## Build our reset vector (This is where linuxBIOS is entered)
|
## Build our reset vector (This is where linuxBIOS is entered)
|
||||||
##
|
##
|
||||||
if USE_FALLBACK_IMAGE
|
if USE_FALLBACK_IMAGE
|
||||||
mainboardinit cpu/i386/reset16.inc
|
mainboardinit cpu/x86/16bit/reset16.inc
|
||||||
ldscript /cpu/i386/reset16.lds
|
ldscript /cpu/x86/16bit/reset16.lds
|
||||||
else
|
else
|
||||||
mainboardinit cpu/i386/reset32.inc
|
mainboardinit cpu/x86/32bit/reset32.inc
|
||||||
ldscript /cpu/i386/reset32.lds
|
ldscript /cpu/x86/32bit/reset32.lds
|
||||||
end
|
end
|
||||||
|
|
||||||
### Should this be in the northbridge code?
|
### Should this be in the northbridge code?
|
||||||
|
|
@ -219,11 +92,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
|
||||||
mainboardinit arch/i386/lib/id.inc
|
mainboardinit arch/i386/lib/id.inc
|
||||||
ldscript /arch/i386/lib/id.lds
|
ldscript /arch/i386/lib/id.lds
|
||||||
|
|
||||||
##
|
|
||||||
## Setup our mtrrs
|
|
||||||
##
|
|
||||||
mainboardinit cpu/k8/earlymtrr.inc
|
|
||||||
|
|
||||||
###
|
###
|
||||||
### This is the early phase of linuxBIOS startup
|
### This is the early phase of linuxBIOS startup
|
||||||
### Things are delicate and we test to see if we should
|
### Things are delicate and we test to see if we should
|
||||||
|
|
@ -241,9 +109,12 @@ end
|
||||||
##
|
##
|
||||||
## Setup RAM
|
## Setup RAM
|
||||||
##
|
##
|
||||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||||
|
mainboardinit cpu/x86/mmx/enable_mmx.inc
|
||||||
|
mainboardinit cpu/x86/sse/enable_sse.inc
|
||||||
mainboardinit ./auto.inc
|
mainboardinit ./auto.inc
|
||||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
mainboardinit cpu/x86/sse/disable_sse.inc
|
||||||
|
mainboardinit cpu/x86/mmx/disable_mmx.inc
|
||||||
|
|
||||||
##
|
##
|
||||||
## Include the secondary Configuration files
|
## Include the secondary Configuration files
|
||||||
|
|
@ -251,7 +122,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||||
dir /pc80
|
dir /pc80
|
||||||
config chip.h
|
config chip.h
|
||||||
|
|
||||||
chip northbridage/amd/amdk8 # mc0
|
chip northbridge/amd/amdk8 # mc0
|
||||||
device pci_domain 0 on
|
device pci_domain 0 on
|
||||||
device pci 18.0 on end # LDT 0
|
device pci 18.0 on end # LDT 0
|
||||||
device pci 18.0 on end # LDT1
|
device pci 18.0 on end # LDT1
|
||||||
|
|
@ -273,7 +144,7 @@ chip northbridage/amd/amdk8 # mc0
|
||||||
device pci 1.0 off end
|
device pci 1.0 off end
|
||||||
end
|
end
|
||||||
device pci 1.0 on
|
device pci 1.0 on
|
||||||
chip superio/windond/w83627hf
|
chip superio/winbond/w83627hf
|
||||||
device pnp 2e.0 on # Floppy
|
device pnp 2e.0 on # Floppy
|
||||||
io 0x60 = 0x3f0
|
io 0x60 = 0x3f0
|
||||||
irq 0x70 = 6
|
irq 0x70 = 6
|
||||||
|
|
@ -328,7 +199,7 @@ chip northbridage/amd/amdk8 # mc0
|
||||||
device pci 19.3 on end
|
device pci 19.3 on end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
device apci_cluster 0 on
|
device apic_cluster 0 on
|
||||||
chip cpu/amd/socket_940
|
chip cpu/amd/socket_940
|
||||||
device apic 0 on end
|
device apic 0 on end
|
||||||
end
|
end
|
||||||
|
|
@ -338,10 +209,3 @@ chip northbridage/amd/amdk8 # mc0
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
##
|
|
||||||
## Include the old serial code for those few places that still need it.
|
|
||||||
##
|
|
||||||
mainboardinit pc80/serial.inc
|
|
||||||
mainboardinit arch/i386/lib/console.inc
|
|
||||||
mainboardinit cpu/i386/bist32_fail.inc
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,210 @@
|
||||||
|
uses HAVE_MP_TABLE
|
||||||
|
uses HAVE_PIRQ_TABLE
|
||||||
|
uses USE_FALLBACK_IMAGE
|
||||||
|
uses HAVE_FALLBACK_BOOT
|
||||||
|
uses HAVE_HARD_RESET
|
||||||
|
uses HARD_RESET_BUS
|
||||||
|
uses HARD_RESET_DEVICE
|
||||||
|
uses HARD_RESET_FUNCTION
|
||||||
|
uses IRQ_SLOT_COUNT
|
||||||
|
uses HAVE_OPTION_TABLE
|
||||||
|
uses CONFIG_MAX_CPUS
|
||||||
|
uses CONFIG_IOAPIC
|
||||||
|
uses CONFIG_SMP
|
||||||
|
uses FALLBACK_SIZE
|
||||||
|
uses ROM_SIZE
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_IMAGE_SIZE
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_SECTION_OFFSET
|
||||||
|
uses CONFIG_ROM_STREAM
|
||||||
|
uses CONFIG_ROM_STREAM_START
|
||||||
|
uses PAYLOAD_SIZE
|
||||||
|
uses _ROMBASE
|
||||||
|
uses XIP_ROM_SIZE
|
||||||
|
uses XIP_ROM_BASE
|
||||||
|
uses STACK_SIZE
|
||||||
|
uses HEAP_SIZE
|
||||||
|
uses USE_OPTION_TABLE
|
||||||
|
uses LB_CKS_RANGE_START
|
||||||
|
uses LB_CKS_RANGE_END
|
||||||
|
uses LB_CKS_LOC
|
||||||
|
uses MAINBOARD_PART_NUMBER
|
||||||
|
uses MAINBOARD_VENDOR
|
||||||
|
uses MAINBOARD
|
||||||
|
uses LINUXBIOS_EXTRA_VERSION
|
||||||
|
uses _RAMBASE
|
||||||
|
uses CC
|
||||||
|
uses HOSTCC
|
||||||
|
uses TTYS0_BAUD
|
||||||
|
uses TTYS0_BASE
|
||||||
|
uses TTYS0_LCS
|
||||||
|
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||||
|
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||||
|
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||||
|
uses CONFIG_CONSOLE_SERIAL8250
|
||||||
|
|
||||||
|
|
||||||
|
###
|
||||||
|
### Build options
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||||
|
##
|
||||||
|
default ROM_SIZE=524288
|
||||||
|
|
||||||
|
##
|
||||||
|
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||||
|
##
|
||||||
|
default FALLBACK_SIZE=131072
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code for the fallback boot
|
||||||
|
##
|
||||||
|
default HAVE_FALLBACK_BOOT=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to reset the motherboard from linuxBIOS
|
||||||
|
##
|
||||||
|
default HAVE_HARD_RESET=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Funky hard reset implementation
|
||||||
|
##
|
||||||
|
default HARD_RESET_BUS=1
|
||||||
|
default HARD_RESET_DEVICE=4
|
||||||
|
default HARD_RESET_FUNCTION=0
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a programmable irq routing table
|
||||||
|
##
|
||||||
|
default HAVE_PIRQ_TABLE=1
|
||||||
|
default IRQ_SLOT_COUNT=9
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export an x86 MP table
|
||||||
|
## Useful for specifying IRQ routing values
|
||||||
|
##
|
||||||
|
default HAVE_MP_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a CMOS option table
|
||||||
|
##
|
||||||
|
default HAVE_OPTION_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||||
|
##
|
||||||
|
default LB_CKS_RANGE_START=49
|
||||||
|
default LB_CKS_RANGE_END=122
|
||||||
|
default LB_CKS_LOC=123
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code for SMP support
|
||||||
|
## Only worry about 2 micro processors
|
||||||
|
##
|
||||||
|
default CONFIG_SMP=1
|
||||||
|
default CONFIG_MAX_CPUS=2
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to setup a generic IOAPIC
|
||||||
|
##
|
||||||
|
default CONFIG_IOAPIC=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Clean up the motherboard id strings
|
||||||
|
##
|
||||||
|
default MAINBOARD_PART_NUMBER="SERENADE"
|
||||||
|
default MAINBOARD_VENDOR="AMD"
|
||||||
|
|
||||||
|
###
|
||||||
|
### LinuxBIOS layout values
|
||||||
|
###
|
||||||
|
|
||||||
|
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||||
|
default ROM_IMAGE_SIZE = 65536
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 8K stack
|
||||||
|
##
|
||||||
|
default STACK_SIZE=0x2000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 16K heap
|
||||||
|
##
|
||||||
|
default HEAP_SIZE=0x4000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Only use the option table in a normal image
|
||||||
|
##
|
||||||
|
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||||
|
|
||||||
|
##
|
||||||
|
## LinuxBIOS C code runs at this location in RAM
|
||||||
|
##
|
||||||
|
default _RAMBASE=0x00004000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Load the payload from the ROM
|
||||||
|
##
|
||||||
|
default CONFIG_ROM_STREAM = 1
|
||||||
|
|
||||||
|
###
|
||||||
|
### Defaults of options that you may want to override in the target config file
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## The default compiler
|
||||||
|
##
|
||||||
|
default CC="gcc -m32"
|
||||||
|
default HOSTCC="gcc"
|
||||||
|
|
||||||
|
##
|
||||||
|
## The Serial Console
|
||||||
|
##
|
||||||
|
|
||||||
|
# To Enable the Serial Console
|
||||||
|
default CONFIG_CONSOLE_SERIAL8250=1
|
||||||
|
|
||||||
|
## Select the serial console baud rate
|
||||||
|
default TTYS0_BAUD=115200
|
||||||
|
#default TTYS0_BAUD=57600
|
||||||
|
#default TTYS0_BAUD=38400
|
||||||
|
#default TTYS0_BAUD=19200
|
||||||
|
#default TTYS0_BAUD=9600
|
||||||
|
#default TTYS0_BAUD=4800
|
||||||
|
#default TTYS0_BAUD=2400
|
||||||
|
#default TTYS0_BAUD=1200
|
||||||
|
|
||||||
|
# Select the serial console base port
|
||||||
|
default TTYS0_BASE=0x3f8
|
||||||
|
|
||||||
|
# Select the serial protocol
|
||||||
|
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||||
|
default TTYS0_LCS=0x3
|
||||||
|
|
||||||
|
##
|
||||||
|
### Select the linuxBIOS loglevel
|
||||||
|
##
|
||||||
|
## EMERG 1 system is unusable
|
||||||
|
## ALERT 2 action must be taken immediately
|
||||||
|
## CRIT 3 critical conditions
|
||||||
|
## ERR 4 error conditions
|
||||||
|
## WARNING 5 warning conditions
|
||||||
|
## NOTICE 6 normal but significant condition
|
||||||
|
## INFO 7 informational
|
||||||
|
## DEBUG 8 debug-level messages
|
||||||
|
## SPEW 9 Way too many details
|
||||||
|
|
||||||
|
## Request this level of debugging output
|
||||||
|
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||||
|
## At a maximum only compile in this level of debugging
|
||||||
|
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||||
|
|
||||||
|
##
|
||||||
|
## Select power on after power fail setting
|
||||||
|
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||||
|
|
||||||
|
### End Options.lb
|
||||||
|
end
|
||||||
Loading…
Reference in New Issue