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nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate files 

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ib1da100ba24de30256b3e80e380deb9c9ef4879e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-09-15 00:36:15 +02:00
parent 63c0dc9dba
commit 587699822c
3 changed files with 74 additions and 58 deletions
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60
src/northbridge/intel/ironlake/ironlake.h
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@ -120,23 +120,7 @@
#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
#define EPPVCCAP1 0x004 /* 32bit */ #include "registers/epbar.h"
#define EPPVCCAP2 0x008 /* 32bit */
#define EPVC0RCAP 0x010 /* 32bit */
#define EPVC0RCTL 0x014 /* 32bit */
#define EPVC0RSTS 0x01a /* 16bit */
#define EPVC1RCAP 0x01c /* 32bit */
#define EPVC1RCTL 0x020 /* 32bit */
#define EPVC1RSTS 0x026 /* 16bit */
#define EPESD 0x044 /* 32bit */
#define EPLE1D 0x050 /* 32bit */
#define EPLE1A 0x058 /* 64bit */
#define EPLE2D 0x060 /* 32bit */
#define EPLE2A 0x068 /* 64bit */
/* /*
* DMIBAR * DMIBAR
@ -146,47 +130,7 @@
#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
#define DMIVCECH 0x000 /* 32bit */ #include "registers/dmibar.h"
#define DMIPVCCAP1 0x004 /* 32bit */
#define DMIPVCCAP2 0x008 /* 32bit */
#define DMIPVCCCTL 0x00c /* 16bit */
#define DMIVC0RCAP 0x010 /* 32bit */
#define DMIVC0RCTL 0x014 /* 32bit */
#define DMIVC0RSTS 0x01a /* 16bit */
#define VC0NP (1 << 1)
#define DMIVC1RCAP 0x01c /* 32bit */
#define DMIVC1RCTL 0x020 /* 32bit */
#define DMIVC1RSTS 0x026 /* 16bit */
#define VC1NP (1 << 1)
#define DMIVCPRCAP 0x028 /* 32bit */
#define DMIVCPRCTL 0x02c /* 32bit */
#define DMIVCPRSTS 0x032 /* 16bit */
#define VCPNP (1 << 1)
#define DMIVCMRCAP 0x034 /* 32bit */
#define DMIVCMRCTL 0x038 /* 32bit */
#define DMIVCMRSTS 0x03e /* 16bit */
#define VCMNP (1 << 1)
#define DMILE1D 0x050 /* 32bit */
#define DMILE1A 0x058 /* 64bit */
#define DMILE2D 0x060 /* 32bit */
#define DMILE2A 0x068 /* 64bit */
#define DMILCAP 0x084 /* 32bit */
#define DMILCTL 0x088 /* 16bit */
#define DMILSTS 0x08a /* 16bit */
#define DMIUESTS 0x1c4 /* 32bit */
#define DMICESTS 0x1d0 /* 32bit */
#define DMICC 0x208 /* 32bit */
#define DMILLTC 0x238 /* 32bit */
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__

48
src/northbridge/intel/ironlake/registers/dmibar.h Normal file
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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __IRONLAKE_REGISTERS_DMIBAR_H__
#define __IRONLAKE_REGISTERS_DMIBAR_H__
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
#define DMIPVCCAP2 0x008 /* 32bit */
#define DMIPVCCCTL 0x00c /* 16bit */
#define DMIVC0RCAP 0x010 /* 32bit */
#define DMIVC0RCTL 0x014 /* 32bit */
#define DMIVC0RSTS 0x01a /* 16bit */
#define VC0NP (1 << 1)
#define DMIVC1RCAP 0x01c /* 32bit */
#define DMIVC1RCTL 0x020 /* 32bit */
#define DMIVC1RSTS 0x026 /* 16bit */
#define VC1NP (1 << 1)
#define DMIVCPRCAP 0x028 /* 32bit */
#define DMIVCPRCTL 0x02c /* 32bit */
#define DMIVCPRSTS 0x032 /* 16bit */
#define VCPNP (1 << 1)
#define DMIVCMRCAP 0x034 /* 32bit */
#define DMIVCMRCTL 0x038 /* 32bit */
#define DMIVCMRSTS 0x03e /* 16bit */
#define VCMNP (1 << 1)
#define DMILE1D 0x050 /* 32bit */
#define DMILE1A 0x058 /* 64bit */
#define DMILE2D 0x060 /* 32bit */
#define DMILE2A 0x068 /* 64bit */
#define DMILCAP 0x084 /* 32bit */
#define DMILCTL 0x088 /* 16bit */
#define DMILSTS 0x08a /* 16bit */
#define DMIUESTS 0x1c4 /* 32bit */
#define DMICESTS 0x1d0 /* 32bit */
#define DMICC 0x208 /* 32bit */
#define DMILLTC 0x238 /* 32bit */
#endif /* __IRONLAKE_REGISTERS_DMIBAR_H__ */

24
src/northbridge/intel/ironlake/registers/epbar.h Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __IRONLAKE_REGISTERS_EPBAR_H__
#define __IRONLAKE_REGISTERS_EPBAR_H__
#define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */
#define EPVC0RCAP 0x010 /* 32bit */
#define EPVC0RCTL 0x014 /* 32bit */
#define EPVC0RSTS 0x01a /* 16bit */
#define EPVC1RCAP 0x01c /* 32bit */
#define EPVC1RCTL 0x020 /* 32bit */
#define EPVC1RSTS 0x026 /* 16bit */
#define EPESD 0x044 /* 32bit */
#define EPLE1D 0x050 /* 32bit */
#define EPLE1A 0x058 /* 64bit */
#define EPLE2D 0x060 /* 32bit */
#define EPLE2A 0x068 /* 64bit */
#endif /* __IRONLAKE_REGISTERS_EPBAR_H__ */