start of 970 port
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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##
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## CPU initialization
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##
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uses _RAMBASE
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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##
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## Use cache ram for initial setup
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##
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default USE_DCACHE_RAM=1
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## Set dcache ram above linuxbios image
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default DCACHE_RAM_BASE=_RAMBASE+0x100000
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## Dcache size is 32Kb
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default DCACHE_RAM_SIZE=0x8000
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initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc
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/*bsp_970fx/bootlib/init_core.s, pibs_970, pibs_970_1.0 1/14/05 14:58:41*/
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/*----------------------------------------------------------------------------+
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| COPYRIGHT I B M CORPORATION 2002, 2004
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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| US Government Users Restricted Rights - Use, duplication or
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| disclosure restricted by GSA ADP Schedule Contract with
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| IBM Corp.
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| PPC970FX BSP for EPOS
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| Author: Maciej P. Tyrlik
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| Component: Boot library.
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| File: init_core.s
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| Purpose: Basic PPC405 core initialization.
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| Changes:
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| Date: Comment:
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| ----- --------
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| 29-Jan-02 Created MPT
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| 30-Jan-02 Completed MPT
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| 19-Apr-02 Changed some instructions to macros so that new GCC AS worksMPT
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| 23-Apr-02 Removed critical interrupt enabling after rfi MPT
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| 31-Jul-02 Fixed data cache invalidate code MPT
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| 01-Feb-03 Ported to Argan 7XXFX CRB
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| 07-Aug-03 Ported to PPC7XXGX CRB
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| 12-Sep-03 Removed PVR definitions, now in board include file MCG
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| 16-Sep-03 Do not enable HID0[MUM] or L2CR[L2CE] if 7XXGX DD1.0 MCG
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| 31-Oct-03 Enable cache for MV64460 integrated SRAM MCG
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| 07-Jan-04 Initialize FPRs to avoid errata. MCG
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| 10-Feb-04 Port to PPC970FX MPT
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+----------------------------------------------------------------------------*/
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#include <sys/as_archppc.h>
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#include <sys/as_archppc970.h>
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#include <ppc970fx_board.h>
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/*----------------------------------------------------------------------------+
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| Local defines.
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+----------------------------------------------------------------------------*/
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#define INITIAL_SLB_VSID_VAL 0x0000000000000C00
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#define INITIAL_SLB_ESID_VAL 0x0000000008000000
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#define INITIAL_SLB_INVA_VAL 0x0000000000000000
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/*----------------------------------------------------------------------------+
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| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0.
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| Data cahability must be turned on. Instruction cahability must be off.
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+----------------------------------------------------------------------------*/
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function_prolog(init_core)
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/*--------------------------------------------------------------------+
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| Set time base to 0.
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+--------------------------------------------------------------------*/
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addi r4,r0,0x0000
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mtspr SPR_TBU_WRITE,r4
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mtspr SPR_TBL_WRITE,r4
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/*--------------------------------------------------------------------+
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| Set HID1[10] to 0 (instruction cache off) and set HID4[23] to 0 (data
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| cache on), set HID4[DC_SET1] and HID4[DC_SET2] to 0.
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+--------------------------------------------------------------------*/
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LOAD_64BIT_VAL(r4,HID1_EN_IC)
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nor r4,r4,r4
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mfspr r5,SPR_HID1
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isync
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and r5,r5,r4
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mtspr SPR_HID1,r5
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mtspr SPR_HID1,r5
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isync
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LOAD_64BIT_VAL(r4,HID4_RM_CI|HID4_DC_SET1|HID4_DC_SET2)
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nor r4,r4,r4
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mfspr r5,SPR_HID4
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LOAD_64BIT_VAL(r6,HID4_L1DC_FLSH)
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isync
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and r5,r5,r4
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or r5,r5,r6
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sync
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mtspr SPR_HID4,r5
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isync
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/*--------------------------------------------------------------------+
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| Clear the flash invalidate L1 data cache bit in HID4.
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+--------------------------------------------------------------------*/
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nor r6,r6,r6
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and r5,r5,r6
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sync
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mtspr SPR_HID4,r5
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isync
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/*--------------------------------------------------------------------+
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| Clear and set up some registers.
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+--------------------------------------------------------------------*/
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addi r4,r0,0x0000
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mtxer r4
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/*--------------------------------------------------------------------+
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| Invalidate SLB. First load SLB with known values then perform
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| invalidate. Invalidate will clear the D-ERAT and I-ERAT. The SLB
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| is 64 entry fully associative. On power on D-ERAT and I-ERAT are all
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| set to invalid values.
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+--------------------------------------------------------------------*/
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addi r5,r0,SLB_SIZE
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mtctr r5
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LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL)
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LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL)
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addis r8,r0,0x1000
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..slbl: slbmte r6,r7
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addi r6,r6,0x1000
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add r7,r7,r8
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addi r7,r7,0x0001
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bdnz ..slbl
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mtctr r5
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LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL)
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..slbi: slbie r6
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add r6,r6,r8
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bdnz ..slbi
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/*--------------------------------------------------------------------+
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| Load SLB. Following is the initial memory map.
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| Entry(6) ESID(36) VSID
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| 0x0 0x000000000 0x0000000000000 (large page cachable)
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| 0x1 0x00000000F 0x000000000000F (small non-cachable, G)
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| at 0x00000000 there will be 48MB mapped (SDRAM)
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| at 0xF8000000 there will be 16MB mapped (NB)
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| at 0xF4000000 there will be 64KB mapped (I/O space)
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| at 0xFF000000 there will be 16MB or 1MB mapped (FLASH)
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+--------------------------------------------------------------------*/
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addi r6,r0,0x0100
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addis r7,r0,0x0800
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slbmte r6,r7
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addi r6,r0,0x0000
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ori r6,r6,0xF000
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addi r7,r0,0x0001
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oris r7,r7,0xF800
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slbmte r6,r7
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/*--------------------------------------------------------------------+
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| Invalidate all 1024 instruction and data TLBs (4 way)
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+--------------------------------------------------------------------*/
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addi r8,r0,0x0100
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mtspr ctr,r8
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addi r8,r0,0x0000
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..ivt: TLBIEL(r8)
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addi r8,r8,0x1000
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bdnz ..ivt
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ptesync
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/*--------------------------------------------------------------------+
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| Dcbz the page table space. Calculate SDR1 address. Store SDR1
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| address in r30.
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+--------------------------------------------------------------------*/
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mfspr r3,SPR_PIR
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cmpi cr0,1,r3,0x0000
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bne ..cpu1
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addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h
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ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l
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b ..skcpu
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..cpu1: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h
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ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l
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..skcpu:addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h
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ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l
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rlwinm r5,r4,14,14,31
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cntlzw r5,r5
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subfic r5,r5,31
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or r30,r3,r5
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bl .ppcDcbz_area
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/*--------------------------------------------------------------------+
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| Setup 0x00000000FFFFFFFF mask in r29.
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+--------------------------------------------------------------------*/
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addi r29,r0,0x0001
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rldicl r29,r29,32,31
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addi r29,r29,-1
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/*--------------------------------------------------------------------+
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| Setup 48MB of addresses in DRAM in page table (3 large PTE). The
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| parameters to p_ptegg are: r3 = lp, r4 = ea, r5 = sdr1, r6 = vsid.
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+--------------------------------------------------------------------*/
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addi r3,r0,0x0001
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addi r4,r0,0x0000
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ori r5,r30,0x0000
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addi r6,r0,0x0000
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bl .p_ptegg
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addi r4,r0,0x0001
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stw r4,0x0004(r3)
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addi r4,r0,0x0180
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stw r4,0x000C(r3)
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/*--------------------------------------------------------------------+
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| Second 16MB is mapped here.
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+--------------------------------------------------------------------*/
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addi r3,r0,0x0001
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addis r4,r0,0x0100
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ori r5,r30,0x0000
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addi r6,r0,0x0000
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bl .p_ptegg
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addi r4,r0,0x0101
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stw r4,0x0004(r3)
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addis r4,r0,0x0100
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ori r4,r4,0x0180
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stw r4,0x000C(r3)
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/*--------------------------------------------------------------------+
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| Third 16MB is mapped here.
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+--------------------------------------------------------------------*/
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addi r3,r0,0x0001
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addis r4,r0,0x0200
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ori r5,r30,0x0000
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addi r6,r0,0x0000
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bl .p_ptegg
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addi r4,r0,0x0201
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stw r4,0x0004(r3)
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addis r4,r0,0x0200
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ori r4,r4,0x0180
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stw r4,0x000C(r3)
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/*--------------------------------------------------------------------+
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| Setup 64KB of addresses in I/O space (0xF4000000).
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+--------------------------------------------------------------------*/
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addi r3,r0,0x0010
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mtctr r3
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addis r31,r0,0xF400
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and r31,r31,r29
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..aF4: addi r3,r0,0x0000
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ori r4,r31,0x0000
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ori r5,r30,0x0000
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addi r6,r0,0x000F
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bl .p_ptegg
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addi r6,r3,0x0080
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..aF4a: lwz r4,0x0004(r3)
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cmpli cr0,1,r4,0x0000
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beq ..aF4s
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addi r3,r3,0x0010
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cmp cr0,1,r3,r6
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blt ..aF4a
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..aF4h: b ..aF4h
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..aF4s: rlwinm r4,r31,16,4,24
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ori r4,r4,0x0001
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stw r4,0x0004(r3)
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ori r4,r31,0x01AC
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stw r4,0x000C(r3)
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addi r31,r31,0x1000
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bdnz ..aF4
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/*--------------------------------------------------------------------+
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| Setup 16MB of addresses in NB register space (0xF8000000).
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+--------------------------------------------------------------------*/
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addi r3,r0,0x1000
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mtctr r3
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addis r31,r0,0xF800
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and r31,r31,r29
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..aF8: addi r3,r0,0x0000
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ori r4,r31,0x0000
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ori r5,r30,0x0000
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addi r6,r0,0x000F
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bl .p_ptegg
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addi r6,r3,0x0080
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..aF8a: lwz r4,0x0004(r3)
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cmpli cr0,1,r4,0x0000
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beq ..aF8s
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addi r3,r3,0x0010
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cmp cr0,1,r3,r6
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blt ..aF8a
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..aF8h: b ..aF8h
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..aF8s: rlwinm r4,r31,16,4,24
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ori r4,r4,0x0001
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stw r4,0x0004(r3)
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ori r4,r31,0x01AC
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stw r4,0x000C(r3)
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addi r31,r31,0x1000
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bdnz ..aF8
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/*--------------------------------------------------------------------+
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| Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000).
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+--------------------------------------------------------------------*/
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mfspr r3,SPR_HIOR
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LOAD_64BIT_VAL(r4,BOOT_BASE_AS)
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cmpd cr0,r3,r4
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beq ..big
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addi r3,r0,0x0100
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mtctr r3
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addis r31,r0,0xFFF0
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b ..done
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..big: addi r3,r0,0x1000
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mtctr r3
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addis r31,r0,0xFF00
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..done: and r31,r31,r29
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..aFF: addi r3,r0,0x0000
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ori r4,r31,0x0000
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ori r5,r30,0x0000
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addi r6,r0,0x000F
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bl .p_ptegg
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addi r6,r3,0x0080
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..aFFa: lwz r4,0x0004(r3)
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cmpli cr0,1,r4,0x0000
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beq ..aFFs
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addi r3,r3,0x0010
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cmp cr0,1,r3,r6
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blt ..aFFa
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..aFFh: b ..aFFh
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..aFFs: rlwinm r4,r31,16,4,24
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ori r4,r4,0x0001
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stw r4,0x0004(r3)
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ori r4,r31,0x01A3
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stw r4,0x000C(r3)
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addi r31,r31,0x1000
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bdnz ..aFF
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/*--------------------------------------------------------------------+
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| Synchronize after setting up page table.
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+--------------------------------------------------------------------*/
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ptesync
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/*--------------------------------------------------------------------+
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| Set the SDR1 register.
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+--------------------------------------------------------------------*/
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mtspr SPR_SDR1,r30
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/*--------------------------------------------------------------------+
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| Clear SRR0, SRR1.
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+--------------------------------------------------------------------*/
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addi r0,r0,0x0000
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mtspr SPR_SRR0,r0
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mtspr SPR_SRR1,r0
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/*--------------------------------------------------------------------+
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| Setup for subsequent MSR[ME] initialization to enable machine checks
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| and translation.
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+--------------------------------------------------------------------*/
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mfmsr r3
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ori r3,r3,(MSR_ME|MSR_IS|MSR_DS|MSR_FP)
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mtsrr1 r3
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mtmsrd r3,0
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isync
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/*--------------------------------------------------------------------+
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| Setup HID registers (HID0, HID1, HID4, HID5). When HIOR is set to
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| 0 HID0 external time base bit is inherited from current HID0. When
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| HIOR is set to FLASH_BASE_INTEL_AS then HID0 external time base bit
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| is set to 1 in order to indicate that the tiembase is driven by
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| external source. When HIOR is greater than FLASH_BASE_INTEL_AS then
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| HID0 external time base bit is set to 0 in order to indicate that the
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| tiembase is driven from internal clock.
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+--------------------------------------------------------------------*/
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LOAD_64BIT_VAL(r6,HID0_EXT_TB_EN)
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LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS)
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mfspr r5,SPR_HIOR
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cmpdi cr0,r5,0x0000
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beq ..hior0
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cmpd cr0,r5,r7
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beq ..hiorl
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addi r8,r0,0x0000
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b ..hiors
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..hiorl:ori r8,r6,0x0000
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b ..hiors
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..hior0:mfspr r5,SPR_HID0
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and r8,r5,r6
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..hiors:LOAD_64BIT_VAL(r4,HID0_PREFEAR)
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andc r4,r4,r6
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or r4,r4,r8
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sync
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mtspr SPR_HID0,r4
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mfspr r4,SPR_HID0
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mfspr r4,SPR_HID0
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mfspr r4,SPR_HID0
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mfspr r4,SPR_HID0
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mfspr r4,SPR_HID0
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mfspr r4,SPR_HID0
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LOAD_64BIT_VAL(r4,HID1_PREFEAR)
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mtspr SPR_HID1,r4
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mtspr SPR_HID1,r4
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isync
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LOAD_64BIT_VAL(r4,HID4_PREFEAR)
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sync
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mtspr SPR_HID4,r4
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isync
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sync
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LOAD_64BIT_VAL(r4,HID5_PREFEAR)
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mtspr SPR_HID5,r4
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isync
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/*--------------------------------------------------------------------+
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| Synchronize memory accesses (sync).
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+--------------------------------------------------------------------*/
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sync
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LOAD_64BIT_VAL(r0,.init_chip)
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mfspr r1,SPR_HIOR
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or r0,r0,r1
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eieio
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mtspr SPR_SRR0,r0
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rfid
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function_epilog(init_core)
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