qcom: Add i2c driver
Add i2c driver in coreboot. Change-Id: I3d39d0325718fc5dd60da42eb2b87dcc4429bfc2 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Prudhvi Yarlagadda
Patrick Georgi
parent
4e0ec59255
commit
58ed173a2c
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@ -8,6 +8,9 @@ bootblock-y += spi.c
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bootblock-y += mmu.c
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bootblock-y += gpio.c
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bootblock-y += clock.c
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bootblock-y += i2c.c
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bootblock-y += qup.c
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bootblock-y += blsp.c
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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################################################################################
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@ -15,6 +18,9 @@ verstage-y += timer.c
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verstage-y += spi.c
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verstage-y += gpio.c
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verstage-y += clock.c
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verstage-y += i2c.c
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verstage-y += qup.c
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verstage-y += blsp.c
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verstage-$(CONFIG_DRIVERS_UART) += uart.c
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################################################################################
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@ -25,6 +31,9 @@ romstage-y += gpio.c
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romstage-y += clock.c
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romstage-y += usb.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-y += i2c.c
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romstage-y += qup.c
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romstage-y += blsp.c
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################################################################################
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ramstage-y += soc.c
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@ -33,6 +42,9 @@ ramstage-y += spi.c
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ramstage-y += cbmem.c
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ramstage-y += gpio.c
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ramstage-y += clock.c
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ramstage-y += i2c.c
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ramstage-y += qup.c
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ramstage-y += blsp.c
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ramstage-y += usb.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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@ -0,0 +1,65 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 - 2016, 2019 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <device/mmio.h>
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#include <soc/blsp.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/clock.h>
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blsp_return_t blsp_i2c_init(blsp_qup_id_t id)
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{
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void *base;
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switch (id) {
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case BLSP_QUP_ID_1:
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gpio_configure
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(GPIO(24), 2, GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT);
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gpio_configure
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(GPIO(25), 2, GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT);
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break;
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default:
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return BLSP_ID_ERROR;
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}
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clock_configure_i2c(19200000);
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clock_enable_i2c();
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base = blsp_qup_base(id);
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if (!base)
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return BLSP_ID_ERROR;
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/* Configure Mini core to I2C core */
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clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
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return BLSP_SUCCESS;
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}
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@ -0,0 +1,181 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
|
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/i2c_simple.h>
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#include <stdlib.h>
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#include <string.h>
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#include <soc/blsp.h>
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#include <soc/qup.h>
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#include <soc/gpio.h>
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static qup_config_t blsp1_qup0_config = {
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QUP_MINICORE_I2C_MASTER,
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400000,
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19200000,
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QUP_MODE_BLOCK,
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0
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};
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static qup_config_t blsp1_qup1_config = {
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QUP_MINICORE_I2C_MASTER,
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400000,
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19200000,
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QUP_MODE_BLOCK,
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0
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};
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static qup_config_t blsp1_qup2_config = {
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QUP_MINICORE_I2C_MASTER,
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400000,
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19200000,
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QUP_MODE_BLOCK,
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0
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};
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static qup_config_t blsp1_qup3_config = {
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QUP_MINICORE_I2C_MASTER,
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400000,
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19200000,
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QUP_MODE_BLOCK,
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0
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};
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static int i2c_read(uint32_t gsbi_id, uint8_t slave,
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uint8_t *data, int data_len)
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{
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qup_data_t obj;
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qup_return_t qup_ret = 0;
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memset(&obj, 0, sizeof(obj));
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obj.protocol = QUP_MINICORE_I2C_MASTER;
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obj.p.iic.addr = slave;
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obj.p.iic.data_len = data_len;
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obj.p.iic.data = data;
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qup_ret = qup_recv_data(gsbi_id, &obj);
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if (qup_ret != QUP_SUCCESS)
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return 1;
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else
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return 0;
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}
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static int i2c_write(uint32_t gsbi_id, uint8_t slave,
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uint8_t *data, int data_len, uint8_t stop_seq)
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{
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qup_data_t obj;
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qup_return_t qup_ret = 0;
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memset(&obj, 0, sizeof(obj));
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obj.protocol = QUP_MINICORE_I2C_MASTER;
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obj.p.iic.addr = slave;
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obj.p.iic.data_len = data_len;
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obj.p.iic.data = data;
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qup_ret = qup_send_data(gsbi_id, &obj, stop_seq);
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if (qup_ret != QUP_SUCCESS)
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return 1;
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else
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return 0;
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}
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static int i2c_init(blsp_qup_id_t id)
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{
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qup_config_t *qup_config;
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switch (id) {
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case BLSP_QUP_ID_0:
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qup_config = &blsp1_qup0_config;
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break;
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case BLSP_QUP_ID_1:
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qup_config = &blsp1_qup1_config;
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break;
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case BLSP_QUP_ID_2:
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qup_config = &blsp1_qup2_config;
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break;
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case BLSP_QUP_ID_3:
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qup_config = &blsp1_qup3_config;
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break;
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default:
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printk(BIOS_ERR, "QUP configuration not defined for BLSP%d.\n",
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id);
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return 1;
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}
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if (qup_config->initialized)
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return 0;
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if (blsp_i2c_init(id)) {
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printk(BIOS_ERR, "failed to initialize blsp\n");
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return 1;
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}
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if (qup_init(id, qup_config)) {
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printk(BIOS_ERR, "failed to initialize qup\n");
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return 1;
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}
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if (qup_reset_i2c_master_status(id)) {
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printk(BIOS_ERR, "failed to reset i2c master status\n");
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return 1;
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}
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qup_config->initialized = 1;
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return 0;
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}
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int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
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int seg_count)
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{
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struct i2c_msg *seg = segments;
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int ret = 0;
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if (i2c_init(bus))
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return 1;
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while (!ret && seg_count--) {
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if (seg->flags & I2C_M_RD)
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ret = i2c_read(bus, seg->slave, seg->buf, seg->len);
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else
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ret = i2c_write(bus, seg->slave, seg->buf, seg->len,
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(seg_count ? 0 : 1));
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seg++;
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}
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if (ret) {
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qup_set_state(bus, QUP_STATE_RESET);
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return 1;
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}
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return 0;
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}
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@ -0,0 +1,609 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
|
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
|
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
|
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <device/mmio.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <stdlib.h>
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#include <soc/qup.h>
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#define TIMEOUT_CNT 100
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#define QUP_ADDR(id, reg) (blsp_qup_base(id) + (reg))
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#define QUP_DEBUG 0
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#define QUPDBG BIOS_ERR, "\t-> "
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#if QUP_DEBUG
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#define qup_write32(a, v) do { \
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write32(a, v); \
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printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \
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__func__, __LINE__, a, v); \
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} while (0)
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#else
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#define qup_write32 write32
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#endif
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struct i2c_clk_div_fld {
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u32 clk_freq_out;
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u8 fs_div;
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u8 ht_div;
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};
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static struct i2c_clk_div_fld i2c_clk_div_map[] = {
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{100000, 124, 62},
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{400000, 28, 14},
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{1000000, 8, 5},
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};
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static void i2c_set_mstr_clk_ctl(unsigned int id, unsigned int hz)
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{
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int i;
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struct i2c_clk_div_fld *itr = i2c_clk_div_map;
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u8 fs_div = 0;
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u8 ht_div = 0;
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u32 mstr_clk_ctl;
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for (i = 0; i < ARRAY_SIZE(i2c_clk_div_map); ++i, ++itr) {
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if (hz == itr->clk_freq_out) {
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if (!fs_div)
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fs_div = itr->fs_div;
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if (!ht_div)
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ht_div = itr->ht_div;
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break;
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}
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}
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/* format values in clk-ctl cache */
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mstr_clk_ctl = ((ht_div & 0xff) << 16) | (fs_div & 0xff);
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qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), mstr_clk_ctl);
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}
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static qup_return_t qup_i2c_master_status(blsp_qup_id_t id)
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{
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uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS));
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if (read32(QUP_ADDR(id, QUP_ERROR_FLAGS)))
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return QUP_ERR_XFER_FAIL;
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#if QUP_DEBUG
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printk(QUPDBG "%s: 0x%x\n", __func__, reg_val);
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#endif
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if (reg_val & QUP_I2C_INVALID_READ_ADDR)
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return QUP_ERR_I2C_INVALID_SLAVE_ADDR;
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if (reg_val & QUP_I2C_FAILED_MASK)
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return QUP_ERR_I2C_FAILED;
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if (reg_val & QUP_I2C_ARB_LOST)
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return QUP_ERR_I2C_ARB_LOST;
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if (reg_val & QUP_I2C_BUS_ERROR)
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return QUP_ERR_I2C_BUS_ERROR;
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if (reg_val & QUP_I2C_INVALID_WRITE)
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return QUP_ERR_I2C_INVALID_WRITE;
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if (reg_val & QUP_I2C_PACKET_NACK)
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return QUP_ERR_I2C_NACK;
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if (reg_val & QUP_I2C_INVALID_TAG)
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return QUP_ERR_I2C_INVALID_TAG;
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return QUP_SUCCESS;
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}
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static int check_bit_state(uint32_t *reg, int wait_for)
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{
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unsigned int count = TIMEOUT_CNT;
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while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) !=
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(QUP_STATE_VALID | wait_for)) {
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if (count == 0)
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return QUP_ERR_TIMEOUT;
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count--;
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}
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return QUP_SUCCESS;
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}
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/*
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* Check whether GSBIn_QUP State is valid
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*/
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static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned int wait_for)
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{
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return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for);
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}
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qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id)
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{
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/*
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* The I2C_STATUS is a status register.
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* Writing any value clears the status bits.
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*/
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qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS), 0);
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return QUP_SUCCESS;
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}
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static qup_return_t qup_reset_master_status(blsp_qup_id_t id)
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{
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qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS), 0x3C);
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qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS_EN), 0x3C);
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qup_reset_i2c_master_status(id);
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return QUP_SUCCESS;
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}
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|
||||
static qup_return_t qup_fifo_wait_for(blsp_qup_id_t id, uint32_t status)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
unsigned int count = TIMEOUT_CNT;
|
||||
|
||||
while (!(read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status)) {
|
||||
ret = qup_i2c_master_status(id);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (count == 0)
|
||||
return QUP_ERR_TIMEOUT;
|
||||
count--;
|
||||
}
|
||||
|
||||
return QUP_SUCCESS;
|
||||
}
|
||||
|
||||
static qup_return_t qup_fifo_wait_while(blsp_qup_id_t id, uint32_t status)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
unsigned int count = TIMEOUT_CNT;
|
||||
|
||||
while (read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status) {
|
||||
ret = qup_i2c_master_status(id);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (count == 0)
|
||||
return QUP_ERR_TIMEOUT;
|
||||
count--;
|
||||
}
|
||||
|
||||
return QUP_SUCCESS;
|
||||
}
|
||||
|
||||
static inline uint32_t qup_i2c_create_output_tag(int stop, u8 data)
|
||||
{
|
||||
uint32_t tag;
|
||||
|
||||
if (stop)
|
||||
tag = QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data);
|
||||
else
|
||||
tag = QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data);
|
||||
|
||||
return tag;
|
||||
}
|
||||
|
||||
static inline qup_return_t qup_i2c_write_fifo_flush(blsp_qup_id_t id)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
|
||||
qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG);
|
||||
|
||||
mdelay(4); /* TPM seems to need this */
|
||||
|
||||
ret = qup_fifo_wait_while(id, OUTPUT_FIFO_NOT_EMPTY);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qup_i2c_master_status(id);
|
||||
|
||||
if (ret)
|
||||
printk(BIOS_DEBUG, "%s: error\n", __func__);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj,
|
||||
uint8_t stop_seq)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
uint8_t addr = p_tx_obj->p.iic.addr;
|
||||
uint8_t *data_ptr = p_tx_obj->p.iic.data;
|
||||
unsigned int data_len = p_tx_obj->p.iic.data_len;
|
||||
unsigned int idx = 0;
|
||||
uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
|
||||
|
||||
qup_reset_master_status(id);
|
||||
|
||||
qup_write32(QUP_ADDR(id, QUP_MX_OUTPUT_COUNT), data_len + 1);
|
||||
|
||||
qup_set_state(id, QUP_STATE_RUN);
|
||||
|
||||
/*
|
||||
* Since UNPACK enable is set in io mode register, populate 2 tags
|
||||
* for each fifo register.
|
||||
*
|
||||
* Create the first tag as follows, with the start tag and first byte
|
||||
* of the data to be written
|
||||
* +--------+--------+--------+--------+
|
||||
* | STOP / | data | START | ADDR |
|
||||
* |DATA tag| byte | tag | << 1 |
|
||||
* +--------+--------+--------+--------+
|
||||
* rest will be created in the following while loop.
|
||||
*/
|
||||
tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
|
||||
data_ptr[idx]);
|
||||
tag = ((tag << 16) & 0xffff0000) |
|
||||
(QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr));
|
||||
data_len--;
|
||||
idx++;
|
||||
|
||||
qup_write32(fifo, tag);
|
||||
|
||||
while (data_len) {
|
||||
|
||||
tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq,
|
||||
data_ptr[idx]);
|
||||
data_len--;
|
||||
idx++;
|
||||
|
||||
if (data_len) {
|
||||
tag |= qup_i2c_create_output_tag(
|
||||
data_len == 1 && stop_seq,
|
||||
data_ptr[idx]) << 16;
|
||||
data_len--;
|
||||
idx++;
|
||||
}
|
||||
|
||||
qup_write32(fifo, tag);
|
||||
|
||||
ret = qup_i2c_write_fifo_flush(id);
|
||||
|
||||
if (ret) {
|
||||
printk(QUPDBG "%s: error\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = qup_i2c_write_fifo_flush(id);
|
||||
|
||||
qup_set_state(id, QUP_STATE_RESET);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static qup_return_t qup_i2c_write(blsp_qup_id_t id, uint8_t mode,
|
||||
qup_data_t *p_tx_obj, uint8_t stop_seq)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
|
||||
switch (mode) {
|
||||
case QUP_MODE_FIFO:
|
||||
case QUP_MODE_BLOCK:
|
||||
ret = qup_i2c_write_fifo(id, p_tx_obj, stop_seq);
|
||||
break;
|
||||
default:
|
||||
ret = QUP_ERR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
qup_set_state(id, QUP_STATE_RESET);
|
||||
printk(QUPDBG "%s() failed (%d)\n", __func__, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qup_i2c_parse_tag(uint32_t data, uint8_t *data_ptr, uint32_t len)
|
||||
{
|
||||
int i, idx = 0;
|
||||
int max = (len > 2) ? 2 : len;
|
||||
|
||||
for (i = 0; i < max; i++) {
|
||||
switch (QUP_I2C_MI_TAG(data)) {
|
||||
case QUP_I2C_MIDATA_SEQ:
|
||||
data_ptr[idx] = QUP_I2C_DATA(data);
|
||||
idx++;
|
||||
break;
|
||||
case QUP_I2C_MISTOP_SEQ:
|
||||
data_ptr[idx] = QUP_I2C_DATA(data);
|
||||
idx++;
|
||||
return idx;
|
||||
default:
|
||||
printk(QUPDBG "%s: Unexpected tag (0x%x)\n", __func__,
|
||||
QUP_I2C_MI_TAG(data));
|
||||
return -1;
|
||||
}
|
||||
|
||||
data = (data >> 16);
|
||||
}
|
||||
|
||||
return idx;
|
||||
}
|
||||
|
||||
static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
uint8_t addr = p_tx_obj->p.iic.addr;
|
||||
uint8_t *data_ptr = p_tx_obj->p.iic.data;
|
||||
unsigned int data_len = p_tx_obj->p.iic.data_len;
|
||||
unsigned int idx = 0;
|
||||
uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO);
|
||||
|
||||
qup_reset_master_status(id);
|
||||
|
||||
qup_write32(QUP_ADDR(id, QUP_IO_MODES),
|
||||
QUP_UNPACK_EN | QUP_PACK_EN |
|
||||
((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
|
||||
QUP_OUTPUT_MODE_SHFT) |
|
||||
((QUP_MODE_BLOCK & QUP_MODE_MASK) <<
|
||||
QUP_INPUT_MODE_SHFT));
|
||||
|
||||
qup_write32(QUP_ADDR(id, QUP_MX_INPUT_COUNT), data_len);
|
||||
|
||||
qup_set_state(id, QUP_STATE_RUN);
|
||||
|
||||
qup_write32(fifo, (QUP_I2C_START_SEQ |
|
||||
(QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)) |
|
||||
((QUP_I2C_RECV_SEQ | data_len) << 16));
|
||||
|
||||
ret = qup_i2c_write_fifo_flush(id);
|
||||
if (ret) {
|
||||
printk(QUPDBG "%s: OUTPUT_FIFO_NOT_EMPTY\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = qup_fifo_wait_for(id, INPUT_SERVICE_FLAG);
|
||||
if (ret) {
|
||||
printk(QUPDBG "%s: INPUT_SERVICE_FLAG\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
fifo = QUP_ADDR(id, QUP_INPUT_FIFO);
|
||||
|
||||
while (data_len) {
|
||||
uint32_t data;
|
||||
int count;
|
||||
|
||||
data = read32(fifo);
|
||||
mdelay(1);
|
||||
|
||||
count = qup_i2c_parse_tag(data, data_ptr + idx, data_len);
|
||||
|
||||
if (count < 0) {
|
||||
printk(QUPDBG "%s: Cannot parse tag 0x%x\n",
|
||||
__func__, data);
|
||||
qup_set_state(id, QUP_STATE_PAUSE);
|
||||
|
||||
return QUP_ERR_I2C_INVALID_TAG;
|
||||
}
|
||||
|
||||
idx += count;
|
||||
data_len -= count;
|
||||
|
||||
qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG);
|
||||
}
|
||||
|
||||
p_tx_obj->p.iic.data_len = idx;
|
||||
|
||||
qup_write32(QUP_ADDR(id, QUP_MX_READ_COUNT), 0);
|
||||
|
||||
qup_set_state(id, QUP_STATE_RESET);
|
||||
|
||||
return QUP_SUCCESS;
|
||||
}
|
||||
|
||||
static qup_return_t qup_i2c_read(blsp_qup_id_t id, uint8_t mode,
|
||||
qup_data_t *p_tx_obj)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
|
||||
qup_set_state(id, QUP_STATE_RESET);
|
||||
|
||||
switch (mode) {
|
||||
case QUP_MODE_FIFO:
|
||||
case QUP_MODE_BLOCK:
|
||||
ret = qup_i2c_read_fifo(id, p_tx_obj);
|
||||
break;
|
||||
default:
|
||||
ret = QUP_ERR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
qup_set_state(id, QUP_STATE_RESET);
|
||||
printk(QUPDBG "%s() failed (%d)\n", __func__, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
uint32_t reg_val;
|
||||
|
||||
/* Reset the QUP core.*/
|
||||
qup_write32(QUP_ADDR(id, QUP_SW_RESET), 0x1);
|
||||
|
||||
/* Wait till the reset takes effect */
|
||||
ret = qup_wait_for_state(id, QUP_STATE_RESET);
|
||||
if (ret)
|
||||
goto bailout;
|
||||
|
||||
/* Reset the config */
|
||||
qup_write32(QUP_ADDR(id, QUP_CONFIG), 0);
|
||||
|
||||
/* Program the config register */
|
||||
/* Set N value */
|
||||
reg_val = 0x0F;
|
||||
/* Set protocol */
|
||||
switch (config_ptr->protocol) {
|
||||
case QUP_MINICORE_I2C_MASTER:
|
||||
reg_val |= ((config_ptr->protocol &
|
||||
QUP_MINI_CORE_PROTO_MASK) <<
|
||||
QUP_MINI_CORE_PROTO_SHFT);
|
||||
break;
|
||||
default:
|
||||
ret = QUP_ERR_UNSUPPORTED;
|
||||
goto bailout;
|
||||
}
|
||||
reg_val |= QUP_APP_CLK_ON_EN | QUP_CORE_CLK_ON_EN;
|
||||
qup_write32(QUP_ADDR(id, QUP_CONFIG), reg_val);
|
||||
|
||||
/* Choose version 1 tag */
|
||||
qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CONFIG), 0);
|
||||
|
||||
/* Reset i2c clk cntl register */
|
||||
qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), 0);
|
||||
|
||||
/* Set QUP IO Mode */
|
||||
switch (config_ptr->mode) {
|
||||
case QUP_MODE_FIFO:
|
||||
case QUP_MODE_BLOCK:
|
||||
reg_val = QUP_UNPACK_EN | QUP_PACK_EN |
|
||||
((config_ptr->mode & QUP_MODE_MASK) <<
|
||||
QUP_OUTPUT_MODE_SHFT) |
|
||||
((config_ptr->mode & QUP_MODE_MASK) <<
|
||||
QUP_INPUT_MODE_SHFT);
|
||||
break;
|
||||
default:
|
||||
ret = QUP_ERR_UNSUPPORTED;
|
||||
goto bailout;
|
||||
}
|
||||
qup_write32(QUP_ADDR(id, QUP_IO_MODES), reg_val);
|
||||
|
||||
/*Set i2c clk cntl*/
|
||||
i2c_set_mstr_clk_ctl(id, 400000);
|
||||
|
||||
qup_set_state(id, QUP_STATE_RESET);
|
||||
bailout:
|
||||
if (ret)
|
||||
printk(QUPDBG "failed to init qup (%d)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
unsigned int curr_state = read32(QUP_ADDR(id, QUP_STATE));
|
||||
|
||||
if ((state <= QUP_STATE_PAUSE)
|
||||
&& (curr_state & QUP_STATE_VALID_MASK)) {
|
||||
/*
|
||||
* For PAUSE_STATE to RESET_STATE transition,
|
||||
* two writes of 10[binary]) are required for the
|
||||
* transition to complete.
|
||||
*/
|
||||
if (curr_state == QUP_STATE_PAUSE && state == QUP_STATE_RESET) {
|
||||
qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
|
||||
qup_write32(QUP_ADDR(id, QUP_STATE), 0x2);
|
||||
} else {
|
||||
qup_write32(QUP_ADDR(id, QUP_STATE), state);
|
||||
}
|
||||
ret = qup_wait_for_state(id, state);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static qup_return_t qup_i2c_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
|
||||
uint8_t stop_seq)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
|
||||
QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK;
|
||||
|
||||
ret = qup_i2c_write(id, mode, p_tx_obj, stop_seq);
|
||||
if (QUP_DEBUG) {
|
||||
int i;
|
||||
|
||||
printk(BIOS_DEBUG, "i2c tx bus %d device %2.2x:",
|
||||
id, p_tx_obj->p.iic.addr);
|
||||
for (i = 0; i < p_tx_obj->p.iic.data_len; i++)
|
||||
printk(BIOS_DEBUG, " %2.2x", p_tx_obj->p.iic.data[i]);
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj,
|
||||
uint8_t stop_seq)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
|
||||
if (p_tx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
|
||||
QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
|
||||
switch (p_tx_obj->protocol) {
|
||||
case QUP_MINICORE_I2C_MASTER:
|
||||
ret = qup_i2c_send_data(id, p_tx_obj, stop_seq);
|
||||
break;
|
||||
default:
|
||||
ret = QUP_ERR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static qup_return_t qup_i2c_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >>
|
||||
QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK;
|
||||
|
||||
ret = qup_i2c_read(id, mode, p_rx_obj);
|
||||
if (QUP_DEBUG) {
|
||||
int i;
|
||||
|
||||
printk(BIOS_DEBUG, "i2c rxed on bus %d device %2.2x:",
|
||||
id, p_rx_obj->p.iic.addr);
|
||||
for (i = 0; i < p_rx_obj->p.iic.data_len; i++)
|
||||
printk(BIOS_DEBUG, " %2.2x", p_rx_obj->p.iic.data[i]);
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj)
|
||||
{
|
||||
qup_return_t ret = QUP_ERR_UNDEFINED;
|
||||
|
||||
if (p_rx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >>
|
||||
QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) {
|
||||
switch (p_rx_obj->protocol) {
|
||||
case QUP_MINICORE_I2C_MASTER:
|
||||
ret = qup_i2c_recv_data(id, p_rx_obj);
|
||||
break;
|
||||
default:
|
||||
ret = QUP_ERR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
Loading…
Reference in New Issue