soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain
Move the GNB IOAPIC resource from being reported in the GNB PCI device to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the common AMD MADT code will be able to find the resource. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -43,9 +43,6 @@ static void read_resources(struct device *dev)
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* the CPU_CLUSTER.
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* the CPU_CLUSTER.
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*/
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*/
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mmconf_resource(dev, idx++);
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mmconf_resource(dev, idx++);
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/* NB IOAPIC2 resource */
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mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000);
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}
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}
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/**
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/**
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@ -301,6 +298,10 @@ void domain_read_resources(struct device *dev)
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/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
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/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
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reserved_ram_from_to(dev, idx++, mem_useable, tom);
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reserved_ram_from_to(dev, idx++, mem_useable, tom);
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/* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT
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code can find this resource */
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mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000);
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/* If there is memory above 4GiB */
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/* If there is memory above 4GiB */
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if (high_tom >> 32) {
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if (high_tom >> 32) {
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/* 4GiB -> high top usable */
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/* 4GiB -> high top usable */
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