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soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain 

Move the GNB IOAPIC resource from being reported in the GNB PCI device
to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the
common AMD MADT code will be able to find the resource.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Felix Held 2024-01-09 16:59:37 +01:00
parent ba48ca8e4a
commit 5913a54a3b
1 changed files with 4 additions and 3 deletions
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7
src/soc/amd/stoneyridge/northbridge.c
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@ -43,9 +43,6 @@ static void read_resources(struct device *dev)
* the CPU_CLUSTER.
*/
mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */
mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000);
}
/**
@ -301,6 +298,10 @@ void domain_read_resources(struct device *dev)
/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
reserved_ram_from_to(dev, idx++, mem_useable, tom);
/* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT
code can find this resource */
mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000);
/* If there is memory above 4GiB */
if (high_tom >> 32) {
/* 4GiB -> high top usable */