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nb/intel/haswell: Enable DMI ASPM 

On Haswell platforms, the processor and the PCH are two separate dies,
and communicate through a high-speed bus. This is DMI (Direct Media
Interface) on traditional two-package platforms, but single-package
Haswell LP variants use OPI (On-Package Interconnect) instead.

Since OPI is not routed through the mainboard, most link parameters are
static and cannot be changed. OPI self-initializes on boot, anyway.

However, DMI needs to be initialized in firmware. On Haswell, the MRC
initializes the physical DMI link, but things like topology and power
management need to be configured as well. And we don't do that properly.

We enable ASPM on the PCH side of the DMI link, but not on the SA side.
Both sides need to use the same settings, so enable DMI ASPM on the SA.
Clearing the error status bits needs to be done on all Haswell variants.

Tested on Asrock B85M Pro4, still boots.

Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-23 02:37:12 +02:00
parent b82b4314ad
commit 598ec6af98
2 changed files with 52 additions and 0 deletions
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10
src/northbridge/intel/haswell/haswell.h
View File

@ -127,11 +127,21 @@
#define DMILCTL 0x088 /* 16bit */
#define DMILSTS 0x08a /* 16bit */
#define DMILCTL2 0x098 /* 16bit */
#define DMICTL1 0x0f0 /* 32bit */
#define DMICTL2 0x0fc /* 32bit */
#define DMIUESTS 0x1c4 /* 32bit */
#define DMICESTS 0x1d0 /* 32bit */
#define DMICC 0x208 /* 32bit */
#define DMIL0SLAT 0x22c /* 32bit */
#define DMILLTC 0x238 /* 32bit */
#define DMI_AFE_PM_TMR 0xc28 /* 32bit */
#define DMIDRCCFG 0xeb4 /* 32bit */
#ifndef __ASSEMBLER__

42
src/northbridge/intel/haswell/northbridge.c
View File

@ -418,10 +418,52 @@ static void disable_devices(void)
pci_write_config32(host_dev, DEVEN, deven);
}
static void northbridge_dmi_init(void)
{
const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP);
u16 reg16;
u32 reg32;
/* Steps prior to DMI ASPM */
if (is_haswell_h) {
/* Configure DMI De-Emphasis */
reg16 = DMIBAR16(DMILCTL2);
reg16 |= (1 << 6); /* 0b: -6.0 dB, 1b: -3.5 dB */
DMIBAR16(DMILCTL2) = reg16;
reg32 = DMIBAR32(DMIL0SLAT);
reg32 |= (1 << 31);
DMIBAR32(DMIL0SLAT) = reg32;
reg32 = DMIBAR32(DMILLTC);
reg32 |= (1 << 29);
DMIBAR32(DMILLTC) = reg32;
reg32 = DMIBAR32(DMI_AFE_PM_TMR);
reg32 &= ~0x1f;
reg32 |= 0x13;
DMIBAR32(DMI_AFE_PM_TMR) = reg32;
}
/* Clear error status bits */
DMIBAR32(DMIUESTS) = 0xffffffff;
DMIBAR32(DMICESTS) = 0xffffffff;
if (is_haswell_h) {
/* Enable ASPM L0s and L1 on SA link, should happen before PCH link */
reg16 = DMIBAR16(DMILCTL);
reg16 |= (1 << 1) | (1 << 0);
DMIBAR16(DMILCTL) = reg16;
}
}
static void northbridge_init(struct device *dev)
{
u8 bios_reset_cpl, pair;
northbridge_dmi_init();
/* Enable Power Aware Interrupt Routing. */
pair = MCHBAR8(INTRDIRCTL);
pair &= ~0x7; /* Clear 2:0 */