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sb/intel/i82371eb: Constify pci_devfn_t devices 

Change-Id: I9056464b36cde89d2fe88ff27531e467297bed0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-02-15 22:07:22 +01:00 committed by Felix Held
parent d3687cd994
commit 5996eea5af
3 changed files with 3 additions and 6 deletions
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3
src/southbridge/intel/i82371eb/bootblock.c
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@ -30,7 +30,6 @@ static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
void bootblock_early_southbridge_init(void) void bootblock_early_southbridge_init(void)
{ {
u16 reg16; u16 reg16;
pci_devfn_t dev;
/* /*
* Note: The Intel 82371AB/EB/MB ISA device can be on different * Note: The Intel 82371AB/EB/MB ISA device can be on different
@ -39,7 +38,7 @@ void bootblock_early_southbridge_init(void)
* But scanning for the PCI IDs (instead of hardcoding * But scanning for the PCI IDs (instead of hardcoding
* bus/device/function numbers) works on all boards. * bus/device/function numbers) works on all boards.
*/ */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
/* Enable access to the whole ROM, disable ROM write access. */ /* Enable access to the whole ROM, disable ROM write access. */

3
src/southbridge/intel/i82371eb/early_pm.c
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@ -9,12 +9,11 @@
void enable_pm(void) void enable_pm(void)
{ {
pci_devfn_t dev;
u8 reg8; u8 reg8;
u16 reg16; u16 reg16;
/* Get the SMBus/PM device of the 82371AB/EB/MB. */ /* Get the SMBus/PM device of the 82371AB/EB/MB. */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the PM I/O base. */ /* Set the PM I/O base. */

3
src/southbridge/intel/i82371eb/early_smbus.c
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@ -21,12 +21,11 @@ uintptr_t smbus_base(void)
int smbus_enable_iobar(uintptr_t base) int smbus_enable_iobar(uintptr_t base)
{ {
pci_devfn_t dev;
u8 reg8; u8 reg8;
u16 reg16; u16 reg16;
/* Get the SMBus/PM device of the 82371AB/EB/MB. */ /* Get the SMBus/PM device of the 82371AB/EB/MB. */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the SMBus I/O base. */ /* Set the SMBus I/O base. */