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sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_config 

Change-Id: I096ccd0ec224b98038d290422f568666bbede43a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-02-15 21:49:49 +01:00 committed by Felix Held
parent 95231b264d
commit d3687cd994
2 changed files with 7 additions and 11 deletions
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10
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -25,8 +25,6 @@
#define NMI_OFF 0
typedef struct southbridge_intel_ibexpeak_config config_t;
/**
* Set miscellaneous static southbridge features.
*
@ -113,7 +111,7 @@ static void pch_pirq_init(struct device *dev)
static void pch_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
u32 reg32 = 0;
/* An array would be much nicer here, or some
@ -146,7 +144,7 @@ static void pch_power_options(struct device *dev)
u32 reg32;
const char *state;
/* Get the chip configuration */
config_t *config = dev->chip_info;
const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
@ -446,7 +444,7 @@ static void lpc_init(struct device *dev)
static void pch_lpc_read_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
u8 io_index = 0;
/* Get the normal PCI resources of this device. */
@ -521,7 +519,7 @@ static const char *lpc_acpi_name(const struct device *dev)
static void southbridge_fill_ssdt(const struct device *device)
{
struct device *dev = pcidev_on_root(0x1f, 0);
config_t *chip = dev->chip_info;
struct southbridge_intel_ibexpeak_config *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
intel_acpi_gen_def_acpi_pirq(dev);

8
src/southbridge/intel/ibexpeak/sata.c
View File

@ -13,8 +13,6 @@
#include "chip.h"
#include "pch.h"
typedef struct southbridge_intel_ibexpeak_config config_t;
static inline u32 sir_read(struct device *dev, int idx)
{
pci_write_config32(dev, SATA_SIRI, idx);
@ -32,7 +30,7 @@ static void sata_init(struct device *dev)
u32 reg32;
u16 reg16;
/* Get the chip configuration */
config_t *config = dev->chip_info;
const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@ -168,7 +166,7 @@ static void sata_init(struct device *dev)
static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
u16 map = 0;
if (!config)
@ -190,7 +188,7 @@ static void sata_enable(struct device *dev)
static void sata_fill_ssdt(const struct device *dev)
{
config_t *config = dev->chip_info;
const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
}