southbridge/intel: Create common IFD Kconfig and Makefile
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC. This is the start of creating a common interface for all of them. This also allows us to reduce the chipset dependencies for CBFS_SIZE. Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10613 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Martin Roth
parent
6ab0fd0a94
commit
59aa2b191b
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@ -338,10 +338,10 @@ source "src/mainboard/Kconfig"
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config CBFS_SIZE
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hex "Size of CBFS filesystem in ROM"
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default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
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default 0x100000 if HAVE_INTEL_FIRMWARE || \
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NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
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NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \
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NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \
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NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \
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NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || \
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NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \
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SOC_INTEL_BROADWELL
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default 0x200000 if SOC_INTEL_FSP_BAYTRAIL
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@ -378,7 +378,9 @@ source "src/ec/acpi/Kconfig"
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source "src/ec/*/*/Kconfig"
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source "src/drivers/intel/fsp1_0/Kconfig"
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source "src/southbridge/intel/common/firmware/Kconfig"
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source "src/vendorcode/*/Kconfig"
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source "src/arch/*/Kconfig"
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endmenu
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@ -36,14 +36,6 @@ config MAINBOARD_DIR
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string
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default intel/mohonpeak
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config INCLUDE_ME
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bool
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default n
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config LOCK_MANAGEMENT_ENGINE
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bool
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default n
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config MAINBOARD_PART_NUMBER
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string
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default "Mohon Peak CRB"
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@ -0,0 +1,94 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Google Inc.
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc.
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##
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config HAVE_INTEL_FIRMWARE
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bool
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help
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Chipset uses the Intel Firmware Descriptor to describe the
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layout of the SPI ROM chip.
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if HAVE_INTEL_FIRMWARE
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comment "Intel Firmware"
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config HAVE_IFD_BIN
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bool "Add Intel descriptor.bin file"
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help
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The descriptor binary
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config IFD_BIN_PATH
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string "Path and filename of the descriptor.bin file"
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depends on HAVE_IFD_BIN && !BUILD_WITH_FAKE_IFD
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config HAVE_ME_BIN
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bool "Add Intel Management Engine firmware"
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depends on USES_INTEL_ME && HAVE_IFD_BIN
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help
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The Intel processor in the selected system requires a special firmware
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for an integrated controller called Management Engine (ME). The ME
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firmware might be provided in coreboot's 3rdparty/blobs repository. If
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not and if you don't have the firmware elsewhere, you can still
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build coreboot without it. In this case however, you'll have to make
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sure that you don't overwrite your ME firmware on your flash ROM.
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config ME_BIN_PATH
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string "Path to management engine firmware"
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depends on HAVE_ME_BIN
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##### Fake IFD #####
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config BUILD_WITH_FAKE_IFD
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bool "Build with a fake IFD" if !HAVE_IFD_BIN
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help
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If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
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board, you can select this option and coreboot will build without it.
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The resulting coreboot.rom will not contain all parts required
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to get coreboot running on your board. You can however write only the
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BIOS section to your board's flash ROM and keep the other sections
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untouched. Unfortunately the current version of flashrom doesn't
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support this yet. But there is a patch pending [1].
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WARNING: Never write a complete coreboot.rom to your flash ROM if it
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was built with a fake IFD. It just won't work.
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[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
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config IFD_BIOS_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_ME_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_GBE_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_PLATFORM_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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endif #INTEL_FIRMWARE
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@ -0,0 +1,73 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc.
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##
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ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y)
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# Run intermediate steps when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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ifeq ($(CONFIG_HAVE_IFD_BIN),y)
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INTERMEDIATE+=add_intel_firmware
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endif
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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INTERMEDIATE+=add_intel_firmware
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IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
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IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
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$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
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$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
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$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
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else
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IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
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endif
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add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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printf "\n** WARNING **\n"
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printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
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printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
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printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
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printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
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$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
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endif
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=$(IFD_BIN_PATH) \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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ifeq ($(CONFIG_HAVE_ME_BIN),y)
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:$(CONFIG_ME_BIN_PATH) \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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printf " IFDTOOL Locking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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printf " IFDTOOL Unlocking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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PHONY+=add_intel_firmware
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endif
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@ -33,6 +33,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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select COMMON_FADT
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select HAVE_INTEL_FIRMWARE
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select USES_INTEL_ME
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config EHCI_BAR
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hex
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@ -53,35 +55,4 @@ config HPET_MIN_TICKS
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hex
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default 0x80
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if HAVE_FSP_BIN
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config INCLUDE_ME
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bool
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default n
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help
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Include the me.bin and descriptor.bin for Intel PCH.
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This is usually required for the PCH.
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config ME_PATH
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string
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depends on INCLUDE_ME
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help
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The path of the ME and Descriptor files.
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config LOCK_MANAGEMENT_ENGINE
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bool "Lock Management Engine section"
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default n
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depends on INCLUDE_ME
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help
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The Intel Management Engine supports preventing write accesses
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from the host to the Management Engine section in the firmware
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descriptor. If the ME section is locked, it can only be overwritten
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with an external SPI flash programmer. You will want this if you
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want to increase security of your ROM image once you are sure
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that the ME firmware is no longer going to change.
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If unsure, say N.
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endif # HAVE_FSP_BIN
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endif
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@ -20,12 +20,7 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y)
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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ifeq ($(CONFIG_INCLUDE_ME),y)
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INTERMEDIATE+=bd82x6x_add_me
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endif
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subdirs-y += ../common/firmware
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ramstage-y += pch.c
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ramstage-y += azalia.c
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@ -51,27 +46,6 @@ smm-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-y += reset.c
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romstage-y += early_spi.c
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bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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printf " IFDTOOL Locking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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else
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printf " IFDTOOL Unlocking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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PHONY += bd82x6x_add_me
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CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x
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endif
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@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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select HAVE_INTEL_FIRMWARE
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config EHCI_BAR
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hex
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@ -52,21 +53,11 @@ config HPET_MIN_TICKS
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hex
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default 0x80
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if HAVE_FSP_BIN
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config INCLUDE_ME
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bool "Add Intel descriptor.bin file"
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default n
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help
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Include the descriptor.bin for rangeley.
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config ME_PATH
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string "Path to descriptor.bin file"
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depends on INCLUDE_ME
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config IFD_BIN_PATH
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string
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depends on HAVE_IFD_BIN
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default "../intel/mainboard/intel/rangeley"
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help
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The path of the descriptor.bin file.
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endif # HAVE_FSP_BIN
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The path and filename to the descriptor.bin file.
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endif
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@ -20,9 +20,7 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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subdirs-y += ../common/firmware
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ramstage-y += soc.c
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ramstage-y += lpc.c
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@ -39,16 +37,4 @@ romstage-y += romstage.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
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ifeq ($(CONFIG_INCLUDE_ME),y)
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INTERMEDIATE+=rangeley_add_descriptor
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rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL)
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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endif
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PHONY += rangeley_add_descriptor
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endif
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@ -32,6 +32,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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select HAVE_INTEL_FIRMWARE
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select USES_INTEL_ME
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config INTEL_LYNXPOINT_LP
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bool
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@ -59,60 +61,20 @@ config HAVE_IFD_BIN
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default y
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config BUILD_WITH_FAKE_IFD
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bool "Build with a fake IFD"
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bool
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default y if !HAVE_IFD_BIN
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help
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If you don't have an Intel Firmware Descriptor (ifd.bin) for your
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board, you can select this option and coreboot will build without it.
|
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Though, the resulting coreboot.rom will not contain all parts required
|
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to get coreboot running on your board. You can however write only the
|
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BIOS section to your board's flash ROM and keep the other sections
|
||||
untouched. Unfortunately the current version of flashrom doesn't
|
||||
support this yet. But there is a patch pending [1].
|
||||
|
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WARNING: Never write a complete coreboot.rom to your flash ROM if it
|
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was built with a fake IFD. It just won't work.
|
||||
|
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[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
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config IFD_BIOS_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_ME_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_GBE_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_PLATFORM_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_BIN_PATH
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string "Path to intel firmware descriptor"
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string
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depends on !BUILD_WITH_FAKE_IFD
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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|
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config HAVE_ME_BIN
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bool "Add Intel Management Engine firmware"
|
||||
bool
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default y
|
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help
|
||||
The Intel processor in the selected system requires a special firmware
|
||||
for an integrated controller called Management Engine (ME). The ME
|
||||
firmware might be provided in coreboot's 3rdparty/blobs repository. If
|
||||
not and if you don't have the firmware elsewhere, you can still
|
||||
build coreboot without it. In this case however, you'll have to make
|
||||
sure that you don't overwrite your ME firmware on your flash ROM.
|
||||
|
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config ME_BIN_PATH
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string "Path to management engine firmware"
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||||
string
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depends on HAVE_ME_BIN
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
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|
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@ -133,16 +95,7 @@ config FINALIZE_USB_ROUTE_XHCI
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to the XHCI controller during the finalize SMM callback.
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||||
|
||||
config LOCK_MANAGEMENT_ENGINE
|
||||
bool "Lock Management Engine section"
|
||||
bool
|
||||
default n
|
||||
help
|
||||
The Intel Management Engine supports preventing write accesses
|
||||
from the host to the Management Engine section in the firmware
|
||||
descriptor. If the ME section is locked, it can only be overwritten
|
||||
with an external SPI flash programmer. You will want this if you
|
||||
want to increase security of your ROM image once you are sure
|
||||
that the ME firmware is no longer going to change.
|
||||
|
||||
If unsure, say N.
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||||
|
||||
endif
|
||||
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|
|
@ -19,10 +19,7 @@
|
|||
|
||||
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
|
||||
|
||||
# Run an intermediate step when producing coreboot.rom
|
||||
# that adds additional components to the final firmware
|
||||
# image outside of CBFS
|
||||
INTERMEDIATE:=lynxpoint_add_me
|
||||
subdirs-y += ../common/firmware
|
||||
|
||||
ramstage-y += pch.c
|
||||
ramstage-y += azalia.c
|
||||
|
|
@ -66,45 +63,4 @@ ramstage-y += gpio.c
|
|||
smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
|
||||
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
|
||||
IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
|
||||
$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
|
||||
$(addprefix -g ,$(CONFIG_IFD_GBE_SECTION:"%"=%)) \
|
||||
$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
|
||||
else
|
||||
IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
|
||||
endif
|
||||
|
||||
lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
|
||||
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
|
||||
printf "\n** WARNING **\n"
|
||||
printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
|
||||
printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
|
||||
printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
|
||||
printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
|
||||
$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
|
||||
endif
|
||||
printf " DD Adding Intel Firmware Descriptor\n"
|
||||
dd if=$(IFD_BIN_PATH) \
|
||||
of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
|
||||
ifeq ($(CONFIG_HAVE_ME_BIN),y)
|
||||
printf " IFDTOOL me.bin -> coreboot.pre\n"
|
||||
$(objutil)/ifdtool/ifdtool \
|
||||
-i ME:$(CONFIG_ME_BIN_PATH) \
|
||||
$(obj)/coreboot.pre
|
||||
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
|
||||
endif
|
||||
ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
|
||||
printf " IFDTOOL Locking Management Engine\n"
|
||||
$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
|
||||
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
|
||||
else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
|
||||
printf " IFDTOOL Unlocking Management Engine\n"
|
||||
$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
|
||||
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
|
||||
endif
|
||||
|
||||
PHONY += lynxpoint_add_me
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue