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Set SB800 ROM decode size based on kconfig. 

Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/94
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Marc Jones 2011-07-12 23:02:03 -06:00 committed by Peter Stuge
parent 2a561a18de
commit 5a91692466
2 changed files with 3 additions and 4 deletions
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5
src/southbridge/amd/cimx/sb800/bootblock.c
View File

@ -49,10 +49,9 @@ static void enable_rom(void)
dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
pci_io_write_config32(dev, 0x48, dword); pci_io_write_config32(dev, 0x48, dword);
/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ /* Enable rom access */
/* Set the 4MB enable bits */
word = pci_io_read_config16(dev, 0x6c); word = pci_io_read_config16(dev, 0x6c);
word = 0xFFC0; word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
pci_io_write_config16(dev, 0x6c, word); pci_io_write_config16(dev, 0x6c, word);
} }

2
src/southbridge/amd/sb800/bootblock.c
View File

@ -57,7 +57,7 @@ static void sb800_enable_rom(void)
* 0xffe0(0000): 2MB * 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB * 0xffc0(0000): 4MB
*/ */
pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */ /* Enable LPC ROM range end at 0xffff(ffff). */
pci_write_config16(dev, 0x6e, 0xffff); pci_write_config16(dev, 0x6e, 0xffff);
} }