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soc/mediatek/mt8183: Refactor DRAM init by bit fields API 

Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and
other bit field helpers.

Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Hung-Te Lin 2019-09-19 17:49:34 +08:00 committed by Patrick Georgi
parent 31ec0c4fdc
commit 5b29f17ef0
4 changed files with 284 additions and 715 deletions
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20
src/soc/mediatek/mt8183/dramc_init_setting.c
View File

@ -92,10 +92,8 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0);
clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18);
if (ca_dll_mode[chn] == DLL_SLAVE) SET32_BITFIELDS(&ch[chn].ao.dvfsdll, DVFSDLL_R_BYPASS_1ST_DLL_SHU1,
setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1); ca_dll_mode[chn] == DLL_SLAVE);
else
clrbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1);
bool is_master = (ca_dll_mode[chn] == DLL_MASTER); bool is_master = (ca_dll_mode[chn] == DLL_MASTER);
u8 phdet_out = is_master ? 0x0 : 0x1; u8 phdet_out = is_master ? 0x0 : 0x1;
@ -138,7 +136,7 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
/* 26M */ /* 26M */
clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x3 << 4, 0x0 << 4); SET32_BITFIELDS(&ch[chn].phy.misc_cg_ctrl0, MISC_CG_CTRL0_CLK_MEM_SEL, 0);
/* MID FINE_TUNE */ /* MID FINE_TUNE */
clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27));
@ -682,26 +680,26 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank)
setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
dramc_cke_fix_onoff(chn, true, false); dramc_cke_fix_onoff(chn, true, false);
clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQCEN, 1);
if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4)) { if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 4)) {
dramc_dbg("ZQCAL Start fail (time out)\n"); dramc_dbg("ZQCAL Start fail (time out)\n");
return 1; return 1;
} }
clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQCEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQCEN, 0);
udelay(1); udelay(1);
setbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQLATEN, 1);
if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) { if (!wait_us(TIMEOUT_US, read32(&ch[chn].nao.spcmdresp) & 0x1 << 6)) {
dramc_dbg("ZQCAL Latch fail (time out)\n"); dramc_dbg("ZQCAL Latch fail (time out)\n");
return 1; return 1;
} }
clrbits_le32(&ch[chn].ao.spcmd, 0x1 << SPCMD_ZQLATEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_ZQLATEN, 0);
udelay(1); udelay(1);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
write32(regs_bak[i].addr, regs_bak[i].value); write32(regs_bak[i].addr, regs_bak[i].value);

9
src/soc/mediatek/mt8183/dramc_pi_basic_api.c
View File

@ -212,11 +212,10 @@ void dramc_sw_impedance_save_reg(u8 freq_group)
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22,
sw_impedance[ca_term][1] << 22); sw_impedance[ca_term][1] << 22);
clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[3], SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3],
SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK, SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE, 1);
1 << SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT); SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0],
clrbits_le32(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0);
SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK);
clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
} }

345
src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
View File

@ -89,24 +89,23 @@ extern u8 MR13Value;
static void dramc_auto_refresh_switch(u8 chn, bool option) static void dramc_auto_refresh_switch(u8 chn, bool option)
{ {
clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, option ? 0 : 1);
(option ? 0 : 1) << REFCTRL0_REFDIS_SHIFT);
if (!option) { if (!option) {
/* /*
* Because HW will actually disable autorefresh after * Because HW will actually disable autorefresh after
* refresh_queue empty, we need to wait until queue empty. * refresh_queue empty, we need to wait until queue empty.
*/ */
udelay(((read32(&ch[chn].nao.misc_statusa) & udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa,
MISC_STATUSA_REFRESH_QUEUE_CNT_MASK) >> MISC_STATUSA_REFRESH_QUEUE_CNT) * 4);
MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT) * 4);
} }
} }
void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off) void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off)
{ {
clrsetbits_le32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), SET32_BITFIELDS(&ch[chn].ao.ckectrl,
((cke_on ? 1 : 0) << 6) | ((cke_off ? 1 : 0) << 7)); CKECTRL_CKEFIXON, cke_on,
CKECTRL_CKEFIXOFF, cke_off);
} }
void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)
@ -114,17 +113,16 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)
u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl);
dramc_cke_fix_onoff(chn, true, false); dramc_cke_fix_onoff(chn, true, false);
clrsetbits_le32(&ch[chn].ao.mrs, SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx);
MRS_MRSMA_MASK, mr_idx << MRS_MRSMA_SHIFT); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSOP, value);
clrsetbits_le32(&ch[chn].ao.mrs, SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 1);
MRS_MRSOP_MASK, value << MRS_MRSOP_SHIFT);
setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT);
/* Wait MRW command fired */ /* Wait MRW command fired */
while ((read32(&ch[chn].nao.spcmdresp) & 1) == 0) while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE)
== 0)
; ;
clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0);
write32(&ch[chn].ao.ckectrl, ckectrl_bak); write32(&ch[chn].ao.ckectrl, ckectrl_bak);
dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); dramc_dbg("Write MR%d =0x%x\n", mr_idx, value);
} }
@ -132,13 +130,12 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)
static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank,
u8 mr_idx, u8 value) u8 mr_idx, u8 value)
{ {
u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; u32 mrs_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRSRK);
dramc_dbg("Mode reg write rank%d MR%d = 0x%x\n", rank, mr_idx, value); dramc_dbg("Mode reg write rank%d MR%d = 0x%x\n", rank, mr_idx, value);
clrsetbits_le32(&ch[chn].ao.mrs, SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT);
dramc_mode_reg_write(chn, mr_idx, value); dramc_mode_reg_write(chn, mr_idx, value);
clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, mrs_bak);
} }
static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_tune) static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_tune)
@ -225,24 +222,21 @@ static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group,
freq_group == LP4X_DDR2400)) freq_group == LP4X_DDR2400))
write_leveling_move_dqs_instead_of_clk(chn); write_leveling_move_dqs_instead_of_clk(chn);
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0); SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 0);
for (size_t byte = 0; byte < DQS_NUMBER; byte++) { for (size_t byte = 0; byte < DQS_NUMBER; byte++) {
u32 wrlevel_dq_delay = wr_level[chn][rank][byte] + 0x10; u32 wrlevel_dq_delay = wr_level[chn][rank][byte] + 0x10;
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7],
FINE_TUNE_PBYTE_MASK, FINE_TUNE_PBYTE, wr_level[chn][rank][byte]);
wr_level[chn][rank][byte] << FINE_TUNE_PBYTE_SHIFT);
if (wrlevel_dq_delay >= 0x40) { if (wrlevel_dq_delay >= 0x40) {
wrlevel_dq_delay -= 0x40; wrlevel_dq_delay -= 0x40;
move_dramc_tx_dq(chn, rank, byte, 2); move_dramc_tx_dq(chn, rank, byte, 2);
move_dramc_tx_dq_oen(chn, rank, byte, 2); move_dramc_tx_dq_oen(chn, rank, byte, 2);
} }
SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7],
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], FINE_TUNE_DQM, wrlevel_dq_delay,
FINE_TUNE_DQM_MASK | FINE_TUNE_DQ_MASK, FINE_TUNE_DQ, wrlevel_dq_delay);
(wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) |
(wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT));
} }
} }
@ -258,14 +252,15 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group,
if (fast_calib) { if (fast_calib) {
/* Set CLK and CA delay */ /* Set CLK and CA delay */
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
(0x3f << 8) | (0x3f << 24), SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, cmd_dly,
(cmd_dly << 8) | (clk_dly << 24)); SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, clk_dly);
udelay(1); udelay(1);
} }
/* Set CLK and CS delay */ /* Set CLK and CS delay */
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], 0x3f, cs_dly << 0); SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9],
SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly);
/* CBT set vref */ /* CBT set vref */
dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref);
@ -275,17 +270,14 @@ static void dramc_read_dbi_onoff(bool on)
{ {
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
for (size_t b = 0; b < 2; b++) for (size_t b = 0; b < 2; b++)
clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[7],
0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT, SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, on);
(on ? 1 : 0) << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT);
} }
static void dramc_write_dbi_onoff(bool on) static void dramc_write_dbi_onoff(bool onoff)
{ {
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
clrsetbits_le32(&ch[chn].ao.shu[0].wodt, SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt, SHU1_WODT_DBIWR, onoff);
0x1 << SHU1_WODT_DBIWR_SHIFT,
(on ? 1 : 0) << SHU1_WODT_DBIWR_SHIFT);
} }
static void dramc_phy_dcm_2_channel(u8 chn, bool en) static void dramc_phy_dcm_2_channel(u8 chn, bool en)
@ -497,59 +489,59 @@ static void dramc_rx_dqs_isi_pulse_cg_switch(u8 chn, bool flag)
static void dramc_set_rank_engine2(u8 chn, u8 rank) static void dramc_set_rank_engine2(u8 chn, u8 rank)
{ {
setbits_le32(&ch[chn].ao.dramctrl, 0x1 << 1); /* Select CTO_AGENT1_RANK */
clrbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL_MASK); SET32_BITFIELDS(&ch[chn].ao.dramctrl, DRAMCTRL_ADRDECEN_TARKMODE, 1);
clrsetbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK_MASK, SET32_BITFIELDS(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL, 0);
rank << TEST2_4_TESTAGENTRK_SHIFT); SET32_BITFIELDS(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK, rank);
} }
static void dramc_engine2_setpat(u8 chn, bool test_pat) static void dramc_engine2_setpat(u8 chn, bool test_pat)
{ {
clrbits_le32(&ch[chn].ao.test2_4, SET32_BITFIELDS(&ch[chn].ao.test2_4,
(0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT) | TEST2_4_TEST_REQ_LEN1, 0,
(0x1 << TEST2_4_TESTXTALKPAT_SHIFT) | TEST2_4_TESTXTALKPAT, 0,
(0x1 << TEST2_4_TESTAUDMODE_SHIFT) | TEST2_4_TESTAUDMODE, 0,
(0x1 << TEST2_4_TESTAUDBITINV_SHIFT)); TEST2_4_TESTAUDBITINV, 0);
if (!test_pat) { if (!test_pat) {
setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.perfctl0, PERFCTL0_RWOFOEN, 1);
SET32_BITFIELDS(&ch[chn].ao.test2_4,
clrsetbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTSSOPAT, 0,
(0x1 << TEST2_4_TESTSSOPAT_SHIFT) | TEST2_4_TESTSSOXTALKPAT, 0,
(0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT), TEST2_4_TESTXTALKPAT, 1);
(0x1 << TEST2_4_TESTXTALKPAT_SHIFT));
} else { } else {
clrsetbits_le32(&ch[chn].ao.test2_4, SET32_BITFIELDS(&ch[chn].ao.test2_4,
TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, TEST2_4_TESTAUDINIT, 0x11,
(0x11 << 8) | (0xd << 0) | (0x1 << 14)); TEST2_4_TESTAUDINC, 0xd,
TEST2_4_TESTAUDBITINV, 1);
} }
clrsetbits_le32(&ch[chn].ao.test2_3, SET32_BITFIELDS(&ch[chn].ao.test2_3,
(0x1 << TEST2_3_TESTAUDPAT_SHIFT) | TEST2_3_TESTCNT_MASK, TEST2_3_TESTAUDPAT, test_pat, TEST2_3_TESTCNT, 0);
(test_pat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT);
} }
static void dramc_engine2_init(u8 chn, u8 rank, u32 t2_1, u32 t2_2, bool test_pat) static void dramc_engine2_init(u8 chn, u8 rank, u32 t2_1, u32 t2_2, bool test_pat)
{ {
dramc_set_rank_engine2(chn, rank); dramc_set_rank_engine2(chn, rank);
clrbits_le32(&ch[chn].ao.dummy_rd, SET32_BITFIELDS(&ch[chn].ao.dummy_rd,
(0x1 << DUMMY_RD_DQSG_DMYRD_EN_SHIFT) | DUMMY_RD_DQSG_DMYRD_EN, 0,
(0x1 << DUMMY_RD_DQSG_DMYWR_EN_SHIFT) | DUMMY_RD_DQSG_DMYWR_EN, 0,
(0x1 << DUMMY_RD_DUMMY_RD_EN_SHIFT) | DUMMY_RD_DUMMY_RD_EN, 0,
(0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) | DUMMY_RD_SREF_DMYRD_EN, 0,
(0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) | DUMMY_RD_DMY_RD_DBG, 0,
(0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT)); DUMMY_RD_DMY_WR_DBG, 0);
clrbits_le32(&ch[chn].nao.testchip_dma1, 0x1 << 12); SET32_BITFIELDS(&ch[chn].nao.testchip_dma1,
clrbits_le32(&ch[chn].ao.test2_3, TESTCHIP_DMA1_DMA_LP4MATAB_OPT, 0);
(0x1 << TEST2_3_TEST2W_SHIFT) | SET32_BITFIELDS(&ch[chn].ao.test2_3,
(0x1 << TEST2_3_TEST2R_SHIFT) | TEST2_3_TEST2W, 0,
(0x1 << TEST2_3_TEST1_SHIFT)); TEST2_3_TEST2R, 0,
clrsetbits_le32(&ch[chn].ao.test2_0, TEST2_3_TEST1, 0);
TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK, SET32_BITFIELDS(&ch[chn].ao.test2_0, TEST2_0_PAT0, t2_1 >> 24,
((t2_1 >> 24) << TEST2_0_PAT0_SHIFT) | TEST2_0_PAT1, t2_2 >> 24);
((t2_2 >> 24) << TEST2_0_PAT1_SHIFT)); SET32_BITFIELDS(&ch[chn].ao.test2_1, TEST2_1_TEST2_BASE,
clrsetbits_le32(&ch[chn].ao.test2_1, 0xfffffff0, (t2_1 & 0x00ffffff) << 4); t2_1 & 0xffffff);
clrsetbits_le32(&ch[chn].ao.test2_2, 0xfffffff0, (t2_2 & 0x00ffffff) << 4); SET32_BITFIELDS(&ch[chn].ao.test2_2, TEST2_2_TEST2_OFF,
t2_2 & 0xffffff);
dramc_engine2_setpat(chn, test_pat); dramc_engine2_setpat(chn, test_pat);
} }
@ -576,10 +568,10 @@ static void dramc_engine2_compare(u8 chn, enum dram_te_op wr)
if (wr == TE_OP_WRITE_READ_CHECK) { if (wr == TE_OP_WRITE_READ_CHECK) {
dramc_engine2_check_complete(chn, rank_status); dramc_engine2_check_complete(chn, rank_status);
clrbits_le32(&ch[chn].ao.test2_3, (0x1 << TEST2_3_TEST2W_SHIFT) | SET32_BITFIELDS(&ch[chn].ao.test2_3, TEST2_3_TEST2W, 0,
(0x1 << TEST2_3_TEST2R_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT)); TEST2_3_TEST2R, 0, TEST2_3_TEST1, 0);
udelay(1); udelay(1);
setbits_le32(&ch[chn].ao.test2_3, 0x1 << TEST2_3_TEST2W_SHIFT); SET32_BITFIELDS(&ch[chn].ao.test2_3, TEST2_3_TEST2W, 1);
} }
dramc_engine2_check_complete(chn, rank_status); dramc_engine2_check_complete(chn, rank_status);
@ -590,26 +582,20 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr)
u32 result; u32 result;
if (wr == TE_OP_READ_CHECK) { if (wr == TE_OP_READ_CHECK) {
clrbits_le32(&ch[chn].ao.test2_4, SET32_BITFIELDS(&ch[chn].ao.test2_4, TEST2_4_TESTAUDMODE, 0);
0x1 << TEST2_4_TESTAUDMODE_SHIFT); SET32_BITFIELDS(&ch[chn].ao.test2_3,
TEST2_3_TEST2W, 0, TEST2_3_TEST2R, 1, TEST2_3_TEST1, 0);
clrsetbits_le32(&ch[chn].ao.test2_3,
(0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) |
(0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2R_SHIFT);
} else if (wr == TE_OP_WRITE_READ_CHECK) { } else if (wr == TE_OP_WRITE_READ_CHECK) {
clrsetbits_le32(&ch[chn].ao.test2_3, SET32_BITFIELDS(&ch[chn].ao.test2_3,
(0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST2R_SHIFT) | TEST2_3_TEST2W, 1, TEST2_3_TEST2R, 0, TEST2_3_TEST1, 0);
(0x1 << TEST2_3_TEST1_SHIFT), 0x1 << TEST2_3_TEST2W_SHIFT);
} }
dramc_engine2_compare(chn, wr); dramc_engine2_compare(chn, wr);
udelay(1); udelay(1);
result = read32(&ch[chn].nao.cmp_err); result = read32(&ch[chn].nao.cmp_err);
clrbits_le32(&ch[chn].ao.test2_3, SET32_BITFIELDS(&ch[chn].ao.test2_3,
(0x1 << TEST2_3_TEST2W_SHIFT) | TEST2_3_TEST2W, 0, TEST2_3_TEST2R, 0, TEST2_3_TEST1, 0);
(0x1 << TEST2_3_TEST2R_SHIFT) |
(0x1 << TEST2_3_TEST1_SHIFT));
return result; return result;
} }
@ -731,16 +717,16 @@ static void dramc_find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t,
static void dram_phy_reset(u8 chn) static void dram_phy_reset(u8 chn)
{ {
setbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT); SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1);
setbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1);
clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
udelay(1); udelay(1);
setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
clrbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0);
clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT); SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0);
} }
static void dramc_set_gating_mode(u8 chn, bool mode) static void dramc_set_gating_mode(u8 chn, bool mode)
@ -769,22 +755,21 @@ static void dramc_set_gating_mode(u8 chn, bool mode)
static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank)
{ {
clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_PBREFEN, 0);
dramc_hw_gating_onoff(chn, false); dramc_hw_gating_onoff(chn, false);
setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBENCMPEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.stbcal1, STBCAL1_STBENCMPEN, 1);
setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBCNT_LATCH_EN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.stbcal1, STBCAL1_STBCNT_LATCH_EN, 1);
clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_DM4TO1MODE_SHIFT); SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_DM4TO1MODE, 0);
setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTEN, 1);
udelay(4); udelay(4);
setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 1);
udelay(1); udelay(1);
clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0);
clrsetbits_le32(&ch[chn].phy.misc_ctrl1, SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMSTBENCMP_RK,
1 << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT, rank);
rank << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT);
} }
@ -897,22 +882,24 @@ static void dramc_rx_dqs_gating_cal_partial(u8 chn, u8 rank,
for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END;
dly_fine_xt += 4) { dly_fine_xt += 4) {
dramc_set_gating_mode(chn, 0); dramc_set_gating_mode(chn, 0);
write32(&ch[chn].ao.shu[0].rk[rank].dqsien, WRITE32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsien,
dly_fine_xt | (dly_fine_xt << 8)); SHURK_DQSIEN_DQS0IEN, dly_fine_xt,
SHURK_DQSIEN_DQS1IEN, dly_fine_xt);
dram_phy_reset(chn); dram_phy_reset(chn);
setbits_le32(&ch[chn].ao.spcmd, SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 1);
1 << SPCMD_DQSGCNTRST_SHIFT);
udelay(1); udelay(1);
clrbits_le32(&ch[chn].ao.spcmd, SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0);
1 << SPCMD_DQSGCNTRST_SHIFT);
dramc_engine2_run(chn, TE_OP_READ_CHECK); dramc_engine2_run(chn, TE_OP_READ_CHECK);
u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & u32 result_r = READ32_BITFIELD(
MISC_STBERR_RK_R_STBERR_RK_R_MASK; &ch[chn].phy.misc_stberr_rk0_r,
u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & MISC_STBERR_RK_R_STBERR_RK_R);
MISC_STBERR_RK_F_STBERR_RK_F_MASK; u32 result_f = READ32_BITFIELD(
&ch[chn].phy.misc_stberr_rk0_f,
MISC_STBERR_RK_F_STBERR_RK_F);
debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]);
debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff;
debug_cnt[0] &= 0xffff; debug_cnt[0] &= 0xffff;
@ -1066,8 +1053,9 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t, dramc_write_dqs_gating_result(chn, rank, best_coarse_tune2t,
best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1); best_coarse_tune0p5t, best_coarse_tune2t_p1, best_coarse_tune0p5t_p1);
write32(&ch[chn].ao.shu[0].rk[rank].dqsien, WRITE32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsien,
best_fine_tune[0] | (best_fine_tune[1] << 8)); SHURK_DQSIEN_DQS0IEN, best_fine_tune[0],
SHURK_DQSIEN_DQS1IEN, best_fine_tune[1]);
dram_phy_reset(chn); dram_phy_reset(chn);
} }
@ -1080,26 +1068,24 @@ static void dramc_rx_rd_dqc_init(u8 chn, u8 rank)
for (size_t b = 0; b < 2; b++) for (size_t b = 0; b < 2; b++)
clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
clrsetbits_le32(&ch[chn].ao.mrs, SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
setbits_le32(&ch[chn].ao.mpc_option,
0x1 << MPC_OPTION_MPCRKEN_SHIFT);
for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++)
temp_value |= ((0x5555 >> bit) & 0x1) << lpddr_phy_mapping[bit]; temp_value |= ((0x5555 >> bit) & 0x1) << lpddr_phy_mapping[bit];
u16 mr15_golden_value = temp_value & 0xff; u16 mr15_golden_value = temp_value & 0xff;
u16 mr20_golden_value = (temp_value >> 8) & 0xff; u16 mr20_golden_value = (temp_value >> 8) & 0xff;
clrsetbits_le32(&ch[chn].ao.mr_golden, SET32_BITFIELDS(&ch[chn].ao.mr_golden,
MR_GOLDEN_MR15_GOLDEN_MASK | MR_GOLDEN_MR20_GOLDEN_MASK, MR_GOLDEN_MR15_GOLDEN, mr15_golden_value,
(mr15_golden_value << 8) | mr20_golden_value); MR_GOLDEN_MR20_GOLDEN, mr20_golden_value);
} }
static u32 dramc_rx_rd_dqc_run(u8 chn) static u32 dramc_rx_rd_dqc_run(u8 chn)
{ {
u32 loop = 0; u32 loop = 0;
setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmdctrl, SPCMDCTRL_RDDQCDIS, 1);
setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_RDDQCEN, 1);
while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 7))) { while (!wait_us(10, read32(&ch[chn].nao.spcmdresp) & (0x1 << 7))) {
if (loop++ > 10) if (loop++ > 10)
@ -1107,27 +1093,28 @@ static u32 dramc_rx_rd_dqc_run(u8 chn)
} }
u32 result = read32(&ch[chn].nao.rdqc_cmp); u32 result = read32(&ch[chn].nao.rdqc_cmp);
clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_RDDQCEN, 0);
clrbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); SET32_BITFIELDS(&ch[chn].ao.spcmdctrl, SPCMDCTRL_RDDQCDIS, 0);
return result; return result;
} }
static void dramc_rx_rd_dqc_end(u8 chn) static void dramc_rx_rd_dqc_end(u8 chn)
{ {
clrbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, 0);
} }
static void dramc_rx_vref_pre_setting(u8 chn) static void dramc_rx_vref_pre_setting(u8 chn)
{ {
setbits_le32(&ch[chn].phy.b[0].dq[5], 0x1 << 16); SET32_BITFIELDS(&ch[chn].phy.b[0].dq[5], B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
setbits_le32(&ch[chn].phy.b[1].dq[5], 0x1 << 16); SET32_BITFIELDS(&ch[chn].phy.b[1].dq[5], B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
} }
static void dramc_set_rx_vref(u8 chn, u8 vref) static void dramc_set_rx_vref(u8 chn, u8 vref)
{ {
for (size_t b = 0; b < 2; b++) for (size_t b = 0; b < 2; b++)
clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], 0x3f, vref << 0); SET32_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[5],
SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, vref);
dramc_dbg("set rx vref :%d\n", vref); dramc_dbg("set rx vref :%d\n", vref);
} }
@ -1174,35 +1161,31 @@ static void dramc_transfer_dly_tune(u8 chn, u32 dly, u32 adjust_center,
static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val) static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val)
{ {
u32 tmp, mask; int b, dq;
switch (type) { switch (type) {
case RX_DQ: case RX_DQ:
tmp = (val << 24 | val << 16 | val << 8 | val); for (dq = 2; dq < 6; dq++)
for (size_t dq = 2; dq < 6; dq++) { for (b = 0; b < 2; b++)
write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[dq], tmp); WRITE32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[dq],
write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[dq], tmp); SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, val,
} SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, val,
SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, val,
SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val);
break; break;
case RX_DQM: case RX_DQM:
tmp = (val << 8 | val); for (b = 0; b < 2; b++)
mask = SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK | SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[6],
SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK; SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, val,
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6], SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, val);
mask, tmp);
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6],
mask, tmp);
break; break;
case RX_DQS: case RX_DQS:
tmp = (val << 24 | val << 16); for (b = 0; b < 2; b++)
mask = SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK | SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[6],
SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK; SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, val,
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6], SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val);
mask, tmp);
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6],
mask, tmp);
break; break;
default: default:
dramc_show("error calibration type:%d\n", type); dramc_show("error calibration type:%d\n", type);
@ -1251,13 +1234,13 @@ static void dramc_set_tx_dly_factor(u8 chn, u8 rk,
if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) {
for (size_t b = 0; b < 2; b++) for (size_t b = 0; b < 2; b++)
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7],
FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); FINE_TUNE_DQ, dly_tune.fine_tune);
} }
if (type == TX_WIN_DQ_DQM) { if (type == TX_WIN_DQ_DQM) {
for (size_t b = 0; b < 2; b++) for (size_t b = 0; b < 2; b++)
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7], SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rk].b[b].dq[7],
FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); FINE_TUNE_DQM, dly_tune.fine_tune);
} }
} }
@ -1510,10 +1493,10 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type,
0x77777777, dqm_small | (dqm_small_oen << 16)); 0x77777777, dqm_small | (dqm_small_oen << 16));
for (size_t byte = 0; byte < 2; byte++) for (size_t byte = 0; byte < 2; byte++)
clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7], SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[7],
FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, FINE_TUNE_DQ, dqdly_tune[byte].fine_tune,
(dqdly_tune[byte].fine_tune << 8) | FINE_TUNE_DQM, dqmdly_tune[byte].fine_tune);
(dqmdly_tune[byte].fine_tune << 16));
if (use_delay_cell == 1) { if (use_delay_cell == 1) {
for (size_t byte = 0; byte < DQS_NUMBER; byte++) for (size_t byte = 0; byte < DQS_NUMBER; byte++)
write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0],
@ -1944,12 +1927,10 @@ static void dramc_dle_factor_handler(u8 chn, u8 val, u8 freq_group)
u8 start_ext2 = 0, start_ext3 = 0, last_ext2 = 0, last_ext3 = 0; u8 start_ext2 = 0, start_ext3 = 0, last_ext2 = 0, last_ext3 = 0;
val = MAX(val, 2); val = MAX(val, 2);
clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], SET32_BITFIELDS(&ch[chn].ao.shu[0].conf[1],
SHU_CONF1_DATLAT_MASK | SHU_CONF1_DATLAT_DSEL_MASK | SHU_CONF1_DATLAT, val,
SHU_CONF1_DATLAT_DSEL_PHY_MASK, SHU_CONF1_DATLAT_DSEL, val - 2,
(val << SHU_CONF1_DATLAT_SHIFT) | SHU_CONF1_DATLAT_DSEL_PHY, val - 2);
((val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) |
((val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT));
if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600)
start_ext2 = 1; start_ext2 = 1;
@ -1959,10 +1940,13 @@ static void dramc_dle_factor_handler(u8 chn, u8 val, u8 freq_group)
else if (val >= 18) else if (val >= 18)
last_ext2 = 1; last_ext2 = 1;
clrsetbits_le32(&ch[chn].ao.shu[0].pipe, (0x1 << 31) | (0x1 << 30) | (0x1 << 29) | SET32_BITFIELDS(&ch[chn].ao.shu[0].pipe,
(0x1 << 28) | (0x1 << 27) | (0x1 << 26), SHU_PIPE_READ_START_EXTEND1, 1,
(0x1 << 31) | (0x1 << 30) | (start_ext2 << 29) | SHU_PIPE_DLE_LAST_EXTEND1, 1,
(last_ext2 << 28) | (start_ext3 << 27) | (last_ext3 << 26)); SHU_PIPE_READ_START_EXTEND2, start_ext2,
SHU_PIPE_DLE_LAST_EXTEND2, last_ext2,
SHU_PIPE_READ_START_EXTEND3, start_ext3,
SHU_PIPE_DLE_LAST_EXTEND3, last_ext3);
dram_phy_reset(chn); dram_phy_reset(chn);
} }
@ -1974,7 +1958,7 @@ static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group,
u32 datlat_start = 7; u32 datlat_start = 7;
*test_passed = true; *test_passed = true;
best_step = read32(&ch[chn].ao.shu[0].conf[1]) & SHU_CONF1_DATLAT_MASK; best_step = READ32_BITFIELD(&ch[chn].ao.shu[0].conf[1], SHU_CONF1_DATLAT);
dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n", dramc_dbg("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n",
chn, rank, best_step); chn, rank, best_step);
@ -2026,9 +2010,8 @@ static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group,
dramc_dle_factor_handler(chn, best_step, freq_group); dramc_dle_factor_handler(chn, best_step, freq_group);
clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | (0x1 << 3), SET32_BITFIELDS(&ch[chn].ao.padctrl,
(0x1 << PADCTRL_DQIENQKEND_SHIFT) | PADCTRL_DQIENQKEND, 1, PADCTRL_DQIENLATEBEGIN, 1);
(0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT));
return (u8) best_step; return (u8) best_step;
} }
@ -2099,12 +2082,12 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
} }
} }
read_dqsinctl = (read32(&ch[chn].ao.shu[0].rk[0].dqsctl) & read_dqsinctl = READ32_BITFIELD(&ch[chn].ao.shu[0].rk[0].dqsctl,
SHURK_DQSCTL_DQSINCTL_MASK) - dqsinctl; SHURK_DQSCTL_DQSINCTL) - dqsinctl;
rankinctl_root = (read_dqsinctl >= 2) ? (read_dqsinctl - 2) : 0; rankinctl_root = (read_dqsinctl >= 2) ? (read_dqsinctl - 2) : 0;
clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf, read_dqsinctl << 0); SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[0].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl);
clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf, read_dqsinctl << 0); SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[1].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl);
clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,
(0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf, (0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf,
(read_dqsinctl << 28) | (rankinctl_root << 20) | (read_dqsinctl << 28) | (rankinctl_root << 20) |

625
src/soc/mediatek/mt8183/include/soc/dramc_register.h
View File

@ -16,6 +16,7 @@
#ifndef _DRAMC_REGISTER_H_ #ifndef _DRAMC_REGISTER_H_
#define _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_
#include <device/mmio.h>
#include <types.h> #include <types.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
@ -178,88 +179,6 @@ struct dramc_nao_regs {
}; };
check_member(dramc_nao_regs, testmode, 0x0000); check_member(dramc_nao_regs, testmode, 0x0000);
check_member(dramc_nao_regs, lbwdat0, 0x0004);
check_member(dramc_nao_regs, lbwdat1, 0x0008);
check_member(dramc_nao_regs, lbwdat2, 0x000c);
check_member(dramc_nao_regs, lbwdat3, 0x0010);
check_member(dramc_nao_regs, ckphchk, 0x0020);
check_member(dramc_nao_regs, dmmonitor, 0x0024);
check_member(dramc_nao_regs, testchip_dma1, 0x0030);
check_member(dramc_nao_regs, misc_statusa, 0x0080);
check_member(dramc_nao_regs, special_status, 0x0084);
check_member(dramc_nao_regs, spcmdresp, 0x0088);
check_member(dramc_nao_regs, mrr_status, 0x008c);
check_member(dramc_nao_regs, mrr_status2, 0x0090);
check_member(dramc_nao_regs, mrrdata0, 0x0094);
check_member(dramc_nao_regs, mrrdata1, 0x0098);
check_member(dramc_nao_regs, mrrdata2, 0x009c);
check_member(dramc_nao_regs, mrrdata3, 0x00a0);
check_member(dramc_nao_regs, drs_status, 0x00a8);
check_member(dramc_nao_regs, jmeter_st, 0x00bc);
check_member(dramc_nao_regs, tcmdo1lat, 0x00c0);
check_member(dramc_nao_regs, rdqc_cmp, 0x00c4);
check_member(dramc_nao_regs, ckphchk_status, 0x00c8);
check_member(dramc_nao_regs, hwmrr_push2pop_cnt, 0x010c);
check_member(dramc_nao_regs, hwmrr_status, 0x0110);
check_member(dramc_nao_regs, testrpt, 0x0120);
check_member(dramc_nao_regs, cmp_err, 0x0124);
check_member(dramc_nao_regs, test_abit_status1, 0x0128);
check_member(dramc_nao_regs, test_abit_status2, 0x012c);
check_member(dramc_nao_regs, test_abit_status3, 0x0130);
check_member(dramc_nao_regs, test_abit_status4, 0x0134);
check_member(dramc_nao_regs, dqsdly0, 0x0150);
check_member(dramc_nao_regs, dq_cal_max[0], 0x0154);
check_member(dramc_nao_regs, dqs_cal_min[0], 0x0174);
check_member(dramc_nao_regs, dqs_cal_max[0], 0x0194);
check_member(dramc_nao_regs, dqical0, 0x01b4);
check_member(dramc_nao_regs, dqical1, 0x01b8);
check_member(dramc_nao_regs, dqical2, 0x01bc);
check_member(dramc_nao_regs, dqical3, 0x01c0);
check_member(dramc_nao_regs, testchip_dma_status[0], 0x0200);
check_member(dramc_nao_regs, refresh_pop_counter, 0x0300);
check_member(dramc_nao_regs, freerun_26m_counter, 0x0304);
check_member(dramc_nao_regs, dramc_idle_counter, 0x0308);
check_member(dramc_nao_regs, r2r_page_hit_counter, 0x030c);
check_member(dramc_nao_regs, r2r_page_miss_counter, 0x0310);
check_member(dramc_nao_regs, r2r_interbank_counter, 0x0314);
check_member(dramc_nao_regs, r2w_page_hit_counter, 0x0318);
check_member(dramc_nao_regs, r2w_page_miss_counter, 0x031c);
check_member(dramc_nao_regs, r2w_interbank_counter, 0x0320);
check_member(dramc_nao_regs, w2r_page_hit_counter, 0x0324);
check_member(dramc_nao_regs, w2r_page_miss_counter, 0x0328);
check_member(dramc_nao_regs, w2r_interbank_counter, 0x032c);
check_member(dramc_nao_regs, w2w_page_hit_counter, 0x0330);
check_member(dramc_nao_regs, w2w_page_miss_counter, 0x0334);
check_member(dramc_nao_regs, w2w_interbank_counter, 0x0338);
check_member(dramc_nao_regs, dq0_toggle_counter, 0x036c);
check_member(dramc_nao_regs, dq1_toggle_counter, 0x0370);
check_member(dramc_nao_regs, dq2_toggle_counter, 0x0374);
check_member(dramc_nao_regs, dq3_toggle_counter, 0x0378);
check_member(dramc_nao_regs, dq0_toggle_counter_r, 0x037c);
check_member(dramc_nao_regs, dq1_toggle_counter_r, 0x0380);
check_member(dramc_nao_regs, dq2_toggle_counter_r, 0x0384);
check_member(dramc_nao_regs, dq3_toggle_counter_r, 0x0388);
check_member(dramc_nao_regs, read_bytes_counter, 0x038c);
check_member(dramc_nao_regs, write_bytes_counter, 0x0390);
check_member(dramc_nao_regs, dqssamplev, 0x0400);
check_member(dramc_nao_regs, dqsgnwcnt[0], 0x0408);
check_member(dramc_nao_regs, toggle_cnt, 0x0420);
check_member(dramc_nao_regs, dqs0_err_cnt, 0x0424);
check_member(dramc_nao_regs, dq_err_cnt0, 0x0428);
check_member(dramc_nao_regs, dqs1_err_cnt, 0x042c);
check_member(dramc_nao_regs, dq_err_cnt1, 0x0430);
check_member(dramc_nao_regs, dqs2_err_cnt, 0x0434);
check_member(dramc_nao_regs, dq_err_cnt2, 0x0438);
check_member(dramc_nao_regs, dqs3_err_cnt, 0x043c);
check_member(dramc_nao_regs, dq_err_cnt3, 0x0440);
check_member(dramc_nao_regs, iorgcnt, 0x0450);
check_member(dramc_nao_regs, dqsg_retry_state, 0x0454);
check_member(dramc_nao_regs, dqsg_retry_state1, 0x0458);
check_member(dramc_nao_regs, impcal_status1, 0x0460);
check_member(dramc_nao_regs, impcal_status2, 0x0464);
check_member(dramc_nao_regs, dqdrv_status, 0x0468);
check_member(dramc_nao_regs, cmddrv_status, 0x046c);
check_member(dramc_nao_regs, cmddrv1, 0x0470);
check_member(dramc_nao_regs, cmddrv2, 0x0474); check_member(dramc_nao_regs, cmddrv2, 0x0474);
struct dramc_ao_regs_rk { struct dramc_ao_regs_rk {
@ -424,104 +343,6 @@ struct dramc_ao_regs {
}; };
check_member(dramc_ao_regs, ddrconf0, 0x0000); check_member(dramc_ao_regs, ddrconf0, 0x0000);
check_member(dramc_ao_regs, dramctrl, 0x0004);
check_member(dramc_ao_regs, misctl0, 0x0008);
check_member(dramc_ao_regs, perfctl0, 0x000c);
check_member(dramc_ao_regs, arbctl, 0x0010);
check_member(dramc_ao_regs, rstmask, 0x001c);
check_member(dramc_ao_regs, padctrl, 0x0020);
check_member(dramc_ao_regs, ckectrl, 0x0024);
check_member(dramc_ao_regs, drsctrl, 0x0028);
check_member(dramc_ao_regs, rkcfg, 0x0034);
check_member(dramc_ao_regs, dramc_pd_ctrl, 0x0038);
check_member(dramc_ao_regs, clkar, 0x003c);
check_member(dramc_ao_regs, clkctrl, 0x0040);
check_member(dramc_ao_regs, selfref_hwsave_flag, 0x0044);
check_member(dramc_ao_regs, srefctrl, 0x0048);
check_member(dramc_ao_regs, refctrl0, 0x004c);
check_member(dramc_ao_regs, refctrl1, 0x0050);
check_member(dramc_ao_regs, refratre_filter, 0x0054);
check_member(dramc_ao_regs, zqcs, 0x0058);
check_member(dramc_ao_regs, mrs, 0x005c);
check_member(dramc_ao_regs, spcmd, 0x0060);
check_member(dramc_ao_regs, spcmdctrl, 0x0064);
check_member(dramc_ao_regs, ppr_ctrl, 0x0068);
check_member(dramc_ao_regs, mpc_option, 0x006c);
check_member(dramc_ao_regs, refque_cnt, 0x0070);
check_member(dramc_ao_regs, hw_mrr_fun, 0x0074);
check_member(dramc_ao_regs, mrr_bit_mux1, 0x0078);
check_member(dramc_ao_regs, mrr_bit_mux2, 0x007c);
check_member(dramc_ao_regs, mrr_bit_mux3, 0x0080);
check_member(dramc_ao_regs, mrr_bit_mux4, 0x0084);
check_member(dramc_ao_regs, test2_5, 0x008c);
check_member(dramc_ao_regs, test2_0, 0x0090);
check_member(dramc_ao_regs, test2_1, 0x0094);
check_member(dramc_ao_regs, test2_2, 0x0098);
check_member(dramc_ao_regs, test2_3, 0x009c);
check_member(dramc_ao_regs, test2_4, 0x00a0);
check_member(dramc_ao_regs, wdt_dbg_signal, 0x00a4);
check_member(dramc_ao_regs, lbtest, 0x00ac);
check_member(dramc_ao_regs, catraining1, 0x00b0);
check_member(dramc_ao_regs, catraining2, 0x00b4);
check_member(dramc_ao_regs, write_lev, 0x00bc);
check_member(dramc_ao_regs, mr_golden, 0x00c0);
check_member(dramc_ao_regs, slp4_testmode, 0x00c4);
check_member(dramc_ao_regs, dqsoscr, 0x00c8);
check_member(dramc_ao_regs, dummy_rd, 0x00d0);
check_member(dramc_ao_regs, shuctrl, 0x00d4);
check_member(dramc_ao_regs, shuctrl1, 0x00d8);
check_member(dramc_ao_regs, shuctrl2, 0x00dc);
check_member(dramc_ao_regs, shuctrl3, 0x00e0);
check_member(dramc_ao_regs, shustatus, 0x00e4);
check_member(dramc_ao_regs, stbcal, 0x0200);
check_member(dramc_ao_regs, stbcal1, 0x0204);
check_member(dramc_ao_regs, stbcal2, 0x0208);
check_member(dramc_ao_regs, eyescan, 0x020c);
check_member(dramc_ao_regs, dvfsdll, 0x0210);
check_member(dramc_ao_regs, pre_tdqsck[0], 0x0218);
check_member(dramc_ao_regs, pre_tdqsck[1], 0x021c);
check_member(dramc_ao_regs, pre_tdqsck[2], 0x0220);
check_member(dramc_ao_regs, pre_tdqsck[3], 0x0224);
check_member(dramc_ao_regs, impcal, 0x022c);
check_member(dramc_ao_regs, impedamce_ctrl1, 0x0230);
check_member(dramc_ao_regs, impedamce_ctrl2, 0x0234);
check_member(dramc_ao_regs, impedamce_ctrl3, 0x0238);
check_member(dramc_ao_regs, impedamce_ctrl4, 0x023c);
check_member(dramc_ao_regs, dramc_dbg_sel1, 0x0240);
check_member(dramc_ao_regs, dramc_dbg_sel2, 0x0244);
check_member(dramc_ao_regs, shu[0].actim[0], 0x0800);
check_member(dramc_ao_regs, shu[0].actim_xrt, 0x081c);
check_member(dramc_ao_regs, shu[0].ac_time_05t, 0x0820);
check_member(dramc_ao_regs, shu[0].ac_derating0, 0x0824);
check_member(dramc_ao_regs, shu[0].ac_derating1, 0x0828);
check_member(dramc_ao_regs, shu[0].ac_derating_05t, 0x0830);
check_member(dramc_ao_regs, shu[0].conf[0], 0x0840);
check_member(dramc_ao_regs, shu[0].rankctl, 0x0858);
check_member(dramc_ao_regs, shu[0].ckectrl, 0x085c);
check_member(dramc_ao_regs, shu[0].odtctrl, 0x0860);
check_member(dramc_ao_regs, shu[0].impcal1, 0x0864);
check_member(dramc_ao_regs, shu[0].dqsosc_prd, 0x0868);
check_member(dramc_ao_regs, shu[0].dqsoscr, 0x086c);
check_member(dramc_ao_regs, shu[0].dqsoscr2, 0x0870);
check_member(dramc_ao_regs, shu[0].rodtenstb, 0x0874);
check_member(dramc_ao_regs, shu[0].pipe, 0x0878);
check_member(dramc_ao_regs, shu[0].test1, 0x087c);
check_member(dramc_ao_regs, shu[0].selph_ca1, 0x0880);
check_member(dramc_ao_regs, shu[0].selph_dqs0, 0x08a0);
check_member(dramc_ao_regs, shu[0].selph_dqs1, 0x08a4);
check_member(dramc_ao_regs, shu[0].drving[0], 0x08a8);
check_member(dramc_ao_regs, shu[0].wodt, 0x08c0);
check_member(dramc_ao_regs, shu[0].dqsg, 0x08c4);
check_member(dramc_ao_regs, shu[0].scintv, 0x08c8);
check_member(dramc_ao_regs, shu[0].misc, 0x08cc);
check_member(dramc_ao_regs, shu[0].dqs2dq_tx, 0x08d0);
check_member(dramc_ao_regs, shu[0].hwset_mr2, 0x08d4);
check_member(dramc_ao_regs, shu[0].hwset_mr13, 0x08d8);
check_member(dramc_ao_regs, shu[0].hwset_vrcg, 0x08dc);
check_member(dramc_ao_regs, shu[0].rk[0].dqsctl, 0x0A00);
check_member(dramc_ao_regs, shu[0].dqsg_retry, 0x0c54);
check_member(dramc_ao_regs, shu[1].dqsg_retry, 0x1254);
check_member(dramc_ao_regs, shu[2].dqsg_retry, 0x1854);
check_member(dramc_ao_regs, shu[3].dqsg_retry, 0x1e54); check_member(dramc_ao_regs, shu[3].dqsg_retry, 0x1e54);
struct dramc_ddrphy_regs_misc_stberr_rk { struct dramc_ddrphy_regs_misc_stberr_rk {
@ -648,78 +469,6 @@ struct dramc_ddrphy_ao_regs {
}; };
check_member(dramc_ddrphy_ao_regs, pll1, 0x0000); check_member(dramc_ddrphy_ao_regs, pll1, 0x0000);
check_member(dramc_ddrphy_ao_regs, b[0].dll_fine_tune[0], 0x0080);
check_member(dramc_ddrphy_ao_regs, b[0].dq[0], 0x0098);
check_member(dramc_ddrphy_ao_regs, b[0].tx_mck, 0x00d0);
check_member(dramc_ddrphy_ao_regs, ca_dll_fine_tune[0], 0x0180);
check_member(dramc_ddrphy_ao_regs, ca_cmd[0], 0x0198);
check_member(dramc_ddrphy_ao_regs, ca_tx_mck, 0x01d0);
check_member(dramc_ddrphy_ao_regs, misc_extlb[0], 0x0200);
check_member(dramc_ddrphy_ao_regs, dvfs_emi_clk, 0x0260);
check_member(dramc_ddrphy_ao_regs, misc_vref_ctrl, 0x0264);
check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl0, 0x0268);
check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl1, 0x026c);
check_member(dramc_ddrphy_ao_regs, misc_shu_opt, 0x0270);
check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl0, 0x0274);
check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl1, 0x0278);
check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl2, 0x027c);
check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl3, 0x0280);
check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl0, 0x0284);
check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl1, 0x0288);
check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl2, 0x028c);
check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl3, 0x0290);
check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl4, 0x0294);
check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl5, 0x0298);
check_member(dramc_ddrphy_ao_regs, misc_ctrl0, 0x029c);
check_member(dramc_ddrphy_ao_regs, misc_ctrl1, 0x02a0);
check_member(dramc_ddrphy_ao_regs, misc_ctrl2, 0x02a4);
check_member(dramc_ddrphy_ao_regs, misc_ctrl3, 0x02a8);
check_member(dramc_ddrphy_ao_regs, misc_ctrl4, 0x02ac);
check_member(dramc_ddrphy_ao_regs, misc_ctrl5, 0x02b0);
check_member(dramc_ddrphy_ao_regs, misc_extlb_rx[0], 0x02b4);
check_member(dramc_ddrphy_ao_regs, ckmux_sel, 0x0308);
check_member(dramc_ddrphy_ao_regs, misc_rxdvs[0], 0x05e0);
check_member(dramc_ddrphy_ao_regs, misc_rxdvs[1], 0x05e4);
check_member(dramc_ddrphy_ao_regs, misc_rxdvs[2], 0x05e8);
check_member(dramc_ddrphy_ao_regs, rfu_0x5ec, 0x05ec);
check_member(dramc_ddrphy_ao_regs, b0_rxdvs[0], 0x05f0);
check_member(dramc_ddrphy_ao_regs, r[0].b[0].rxdvs[0], 0x0600);
check_member(dramc_ddrphy_ao_regs, b1_rxdvs[0], 0x0670);
check_member(dramc_ddrphy_ao_regs, r[0].b[1].rxdvs[0], 0x0680);
check_member(dramc_ddrphy_ao_regs, ca_rxdvs0, 0x06F0);
check_member(dramc_ddrphy_ao_regs, r0_ca_rxdvs[0], 0x0700);
check_member(dramc_ddrphy_ao_regs, r[1].b[1].rxdvs[0], 0x0880);
check_member(dramc_ddrphy_ao_regs, r[1].rxdvs[0], 0x0900);
check_member(dramc_ddrphy_ao_regs, shu[0].b[0].dq[0], 0x0c00);
check_member(dramc_ddrphy_ao_regs, shu[0].b[1].dq[6], 0x0C98);
check_member(dramc_ddrphy_ao_regs, shu[0].ca_cmd[0], 0x0d00);
check_member(dramc_ddrphy_ao_regs, shu[0].ca_dll[0], 0x0d34);
check_member(dramc_ddrphy_ao_regs, shu[0].pll[0], 0x0d80);
check_member(dramc_ddrphy_ao_regs, shu[0].misc0, 0x0DF0);
check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].b[0].dq[0], 0x0e00);
check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].ca_cmd[9], 0x0ec4);
check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].b[0].dq[0], 0x0f00);
check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].ca_cmd[9], 0x0fc4);
check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].b[0].dq[0], 0x1000);
check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].ca_cmd[9], 0x10c4);
check_member(dramc_ddrphy_ao_regs, shu[2].b[0].dq[0], 0x1600);
check_member(dramc_ddrphy_ao_regs, shu[2].b[1].dq[0], 0x1680);
check_member(dramc_ddrphy_ao_regs, shu[2].ca_cmd[0], 0x1700);
check_member(dramc_ddrphy_ao_regs, shu[2].ca_dll[0], 0x1734);
check_member(dramc_ddrphy_ao_regs, shu[2].pll[0], 0x1780);
check_member(dramc_ddrphy_ao_regs, shu[2].misc0, 0x17F0);
check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].b[0].dq[0], 0x1800);
check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].ca_cmd[0], 0x18A0);
check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].b[0].dq[0], 0x1900);
check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].ca_cmd[0], 0x19A0);
check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].b[0].dq[0], 0x1A00);
check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].ca_cmd[0], 0x1AA0);
check_member(dramc_ddrphy_ao_regs, shu[3].ca_cmd[0], 0x1C00);
check_member(dramc_ddrphy_ao_regs, shu[3].pll[0], 0x1C80);
check_member(dramc_ddrphy_ao_regs, shu[3].pll20, 0x1CD0);
check_member(dramc_ddrphy_ao_regs, shu[3].misc0, 0x1CF0);
check_member(dramc_ddrphy_ao_regs, shu[3].rk[0].ca_cmd[9], 0x1DC4);
check_member(dramc_ddrphy_ao_regs, shu[3].rk[1].ca_cmd[9], 0x1EC4);
check_member(dramc_ddrphy_ao_regs, shu[3].rk[2].ca_cmd[9], 0x1FC4); check_member(dramc_ddrphy_ao_regs, shu[3].rk[2].ca_cmd[9], 0x1FC4);
struct dramc_ddrphy_nao_regs { struct dramc_ddrphy_nao_regs {
@ -739,12 +488,6 @@ struct dramc_ddrphy_nao_regs {
}; };
check_member(dramc_ddrphy_nao_regs, misc_sta_extlb[0], 0x0); check_member(dramc_ddrphy_nao_regs, misc_sta_extlb[0], 0x0);
check_member(dramc_ddrphy_nao_regs, misc_dq_rxdly_trro[0], 0x080);
check_member(dramc_ddrphy_nao_regs, misc_dqo1, 0x0180);
check_member(dramc_ddrphy_nao_regs, misc_cao1, 0x0184);
check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_dq, 0x0190);
check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_cmd, 0x0194);
check_member(dramc_ddrphy_nao_regs, misc_phy_stben_b[0], 0x0198);
check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_stben_cmd, 0x01A0); check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_stben_cmd, 0x01A0);
struct emi_regs { struct emi_regs {
@ -830,43 +573,6 @@ struct emi_regs {
}; };
check_member(emi_regs, cona, 0x0000); check_member(emi_regs, cona, 0x0000);
check_member(emi_regs, conb, 0x0008);
check_member(emi_regs, conc, 0x0010);
check_member(emi_regs, cond, 0x0018);
check_member(emi_regs, cone, 0x0020);
check_member(emi_regs, conf, 0x0028);
check_member(emi_regs, cong, 0x0030);
check_member(emi_regs, conh, 0x0038);
check_member(emi_regs, conh_2nd, 0x003c);
check_member(emi_regs, coni, 0x0040);
check_member(emi_regs, conj, 0x0048);
check_member(emi_regs, conm, 0x0060);
check_member(emi_regs, conn, 0x0068);
check_member(emi_regs, cono, 0x0070);
check_member(emi_regs, mdct, 0x0078);
check_member(emi_regs, mdct_2nd, 0x007c);
check_member(emi_regs, iocl, 0x00d0);
check_member(emi_regs, iocl_2nd, 0x00d4);
check_member(emi_regs, iocm, 0x00d8);
check_member(emi_regs, iocm_2nd, 0x00dc);
check_member(emi_regs, testb, 0x00e8);
check_member(emi_regs, testc, 0x00f0);
check_member(emi_regs, testd, 0x00f8);
check_member(emi_regs, arba, 0x0100);
check_member(emi_regs, arbb, 0x0108);
check_member(emi_regs, arbc, 0x0110);
check_member(emi_regs, arbd, 0x0118);
check_member(emi_regs, arbe, 0x0120);
check_member(emi_regs, arbf, 0x0128);
check_member(emi_regs, arbg, 0x0130);
check_member(emi_regs, arbh, 0x0138);
check_member(emi_regs, arbi, 0x0140);
check_member(emi_regs, arbi_2nd, 0x0144);
check_member(emi_regs, slct, 0x0158);
check_member(emi_regs, bwct0, 0x05B0);
check_member(emi_regs, bwct0_2nd, 0x06A0);
check_member(emi_regs, bwct0_3rd, 0x0770);
check_member(emi_regs, bwct0_4th, 0x0780);
check_member(emi_regs, bwct0_5th, 0x07B0); check_member(emi_regs, bwct0_5th, 0x07B0);
struct chn_emi_regs { struct chn_emi_regs {
@ -909,26 +615,6 @@ struct chn_emi_regs {
}; };
check_member(chn_emi_regs, chn_cona, 0x0000); check_member(chn_emi_regs, chn_cona, 0x0000);
check_member(chn_emi_regs, chn_conb, 0x0008);
check_member(chn_emi_regs, chn_conc, 0x0010);
check_member(chn_emi_regs, chn_mdct, 0x0018);
check_member(chn_emi_regs, chn_testb, 0x0048);
check_member(chn_emi_regs, chn_testc, 0x0050);
check_member(chn_emi_regs, chn_testd, 0x0058);
check_member(chn_emi_regs, chn_md_pre_mask, 0x0080);
check_member(chn_emi_regs, chn_md_pre_mask_shf, 0x0088);
check_member(chn_emi_regs, chn_arbi, 0x0140);
check_member(chn_emi_regs, chn_arbi_2nd, 0x0144);
check_member(chn_emi_regs, chn_arbj, 0x0148);
check_member(chn_emi_regs, chn_arbj_2nd, 0x014c);
check_member(chn_emi_regs, chn_arbk, 0x0150);
check_member(chn_emi_regs, chn_arbk_2nd, 0x0154);
check_member(chn_emi_regs, chn_slct, 0x0158);
check_member(chn_emi_regs, chn_arb_ref, 0x015c);
check_member(chn_emi_regs, chn_rkarb0, 0x01b0);
check_member(chn_emi_regs, chn_rkarb1, 0x01b4);
check_member(chn_emi_regs, chn_rkarb2, 0x01b8);
check_member(chn_emi_regs, chn_eco3, 0x03fc);
check_member(chn_emi_regs, chn_emi_shf0, 0x0710); check_member(chn_emi_regs, chn_emi_shf0, 0x0710);
struct emi_mpu_regs { struct emi_mpu_regs {
@ -940,245 +626,148 @@ struct emi_mpu_regs {
check_member(emi_mpu_regs, mpu_ctrl, 0x0000); check_member(emi_mpu_regs, mpu_ctrl, 0x0000);
check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800);
enum { DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24)
TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12, DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0)
};
enum { DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22)
MISC_STATUSA_SREF_STATE = 16, DEFINE_BIT(DDRCONF0_RDATRST, 0)
MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT = 24, DEFINE_BIT(PERFCTL0_RWOFOEN, 4)
MISC_STATUSA_REFRESH_QUEUE_CNT_MASK = 0x0f000000,
};
enum { DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3)
DDRCONF0_DM4TO1MODE_SHIFT = 22, DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0)
DDRCONF0_RDATRST_SHIFT = 0,
};
enum { DEFINE_BITFIELD(SHURK_DQSIEN_DQS0IEN, 6, 0)
PERFCTL0_RWOFOEN_SHIFT = 4, DEFINE_BITFIELD(SHURK_DQSIEN_DQS1IEN, 14, 8)
}; DEFINE_BITFIELD(SHURK_DQSIEN_DQS2IEN, 22, 16)
DEFINE_BITFIELD(SHURK_DQSIEN_DQS3IEN, 30, 24)
enum { DEFINE_BIT(REFCTRL0_REFDIS, 29)
PADCTRL_DQIENLATEBEGIN_SHIFT = 3, DEFINE_BIT(REFCTRL0_PBREFEN, 18)
PADCTRL_DQIENQKEND_SHIFT = 0,
PADCTRL_DQIENQKEND_MASK = 0x00000003,
};
enum { DEFINE_BIT(CKECTRL_CKEFIXON, 6)
REFCTRL0_REFDIS_SHIFT = 29, DEFINE_BIT(CKECTRL_CKEFIXOFF, 7)
REFCTRL0_PBREFEN_SHIFT = 18,
};
enum { DEFINE_BITFIELD(MRS_MRSBG, 31, 30)
MRS_MPCRK_SHIFT = 28, DEFINE_BITFIELD(MRS_MPCRK, 29, 28)
MRS_MPCRK_MASK = 0x30000000, DEFINE_BITFIELD(MRS_MRRRK, 27, 26)
MRS_MRSRK_SHIFT = 24, DEFINE_BITFIELD(MRS_MRSRK, 25, 24)
MRS_MRSRK_MASK = 0x03000000, DEFINE_BITFIELD(MRS_MRSBA, 23, 21)
MRS_MRSMA_SHIFT = 8, DEFINE_BITFIELD(MRS_MRSMA, 20, 8)
MRS_MRSMA_MASK = 0x001fff00, DEFINE_BITFIELD(MRS_MRSOP, 7, 0)
MRS_MRSOP_SHIFT = 0,
MRS_MRSOP_MASK = 0x000000ff,
};
enum { DEFINE_BIT(SPCMD_DQSGCNTRST, 9)
SPCMD_DQSGCNTRST_SHIFT = 9, DEFINE_BIT(SPCMD_DQSGCNTEN, 8)
SPCMD_DQSGCNTEN_SHIFT = 8, DEFINE_BIT(SPCMD_ZQLATEN, 6)
SPCMD_RDDQCEN_SHIFT = 7, DEFINE_BIT(SPCMD_RDDQCEN, 7)
SPCMD_ZQLATEN_SHIFT = 6, DEFINE_BIT(SPCMD_ZQCEN, 4)
SPCMD_ZQCEN_SHIFT = 4, DEFINE_BIT(SPCMD_MRWEN, 0)
SPCMD_MRWEN_SHIFT = 0,
};
enum { DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11)
SPCMDCTRL_RDDQCDIS_SHIFT = 11,
};
enum { DEFINE_BIT(MPC_OPTION_MPCRKEN, 17)
MPC_OPTION_MPCRKEN_SHIFT = 17,
};
enum { DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1)
TEST2_0_PAT0_SHIFT = 8,
TEST2_0_PAT0_MASK = 0x0000ff00,
TEST2_0_PAT1_SHIFT = 0,
TEST2_0_PAT1_MASK = 0x000000ff,
};
enum { DEFINE_BITFIELD(MISC_CG_CTRL0_CLK_MEM_SEL, 5, 4)
TEST2_3_TEST2W_SHIFT = 31,
TEST2_3_TEST2R_SHIFT = 30,
TEST2_3_TEST1_SHIFT = 29,
TEST2_3_TESTAUDPAT_SHIFT = 7,
TEST2_3_TESTCNT_SHIFT = 0,
TEST2_3_TESTCNT_MASK = 0x0000000f,
};
enum { DEFINE_BIT(DRAMCTRL_ADRDECEN_TARKMODE, 1)
TEST2_4_TESTAGENTRKSEL_MASK = 0x70000000,
TEST2_4_TESTAGENTRK_SHIFT = 24,
TEST2_4_TESTAGENTRK_MASK = 0x03000000,
TEST2_4_TEST_REQ_LEN1_SHIFT = 17,
TEST2_4_TESTXTALKPAT_SHIFT = 16,
TEST2_4_TESTAUDMODE_SHIFT = 15,
TEST2_4_TESTAUDBITINV_SHIFT = 14,
TEST2_4_TESTAUDINIT_SHIFT = 8,
TEST2_4_TESTAUDINIT_MASK = 0x00001f00,
TEST2_4_TESTSSOXTALKPAT_SHIFT = 7,
TEST2_4_TESTSSOPAT_SHIFT = 6,
TEST2_4_TESTAUDINC_SHIFT = 0,
TEST2_4_TESTAUDINC_MASK = 0x0000001f,
};
enum { DEFINE_BIT(TESTCHIP_DMA1_DMA_LP4MATAB_OPT, 12)
MR_GOLDEN_MR15_GOLDEN_MASK = 0x0000ff00, DEFINE_BITFIELD(TEST2_0_PAT0, 15, 8)
MR_GOLDEN_MR20_GOLDEN_MASK = 0x000000ff, DEFINE_BITFIELD(TEST2_0_PAT1, 7, 0)
};
enum { DEFINE_BITFIELD(TEST2_1_TEST2_BASE, 31, 4)
DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT = 7, DEFINE_BITFIELD(TEST2_2_TEST2_OFF, 31, 4)
};
enum { DEFINE_BIT(TEST2_3_TEST2W, 31)
DUMMY_RD_DQSG_DMYWR_EN_SHIFT = 23, DEFINE_BIT(TEST2_3_TEST2R, 30)
DUMMY_RD_DQSG_DMYRD_EN_SHIFT = 22, DEFINE_BIT(TEST2_3_TEST1, 29)
DUMMY_RD_SREF_DMYRD_EN_SHIFT = 21, DEFINE_BIT(TEST2_3_TESTAUDPAT, 7)
DUMMY_RD_DUMMY_RD_EN_SHIFT = 20, DEFINE_BITFIELD(TEST2_3_TESTCNT, 3, 0)
DUMMY_RD_DMY_RD_DBG_SHIFT = 7,
DUMMY_RD_DMY_WR_DBG_SHIFT = 6,
};
enum { DEFINE_BITFIELD(TEST2_4_TESTAGENTRKSEL, 30, 28)
STBCAL1_STBCNT_LATCH_EN_SHIFT = 11, DEFINE_BITFIELD(TEST2_4_TESTAGENTRK, 25, 24)
STBCAL1_STBENCMPEN_SHIFT = 10, DEFINE_BIT(TEST2_4_TEST_REQ_LEN1, 17)
}; DEFINE_BIT(TEST2_4_TESTXTALKPAT, 16)
DEFINE_BIT(TEST2_4_TESTAUDMODE, 15)
DEFINE_BIT(TEST2_4_TESTAUDBITINV, 14)
DEFINE_BITFIELD(TEST2_4_TESTAUDINIT, 12, 8)
DEFINE_BIT(TEST2_4_TESTSSOXTALKPAT, 7)
DEFINE_BIT(TEST2_4_TESTSSOPAT, 6)
DEFINE_BITFIELD(TEST2_4_TESTAUDINC, 4, 0)
enum { DEFINE_BITFIELD(MR_GOLDEN_MR15_GOLDEN, 15, 8)
SHU_ACTIM_XRT_XRTR2R_SHIFT = 0, DEFINE_BITFIELD(MR_GOLDEN_MR20_GOLDEN, 7, 0)
SHU_ACTIM_XRT_XRTR2R_MASK = 0x0000000f,
};
enum { DEFINE_BIT(DUMMY_RD_DQSG_DMYWR_EN, 23)
SHU_CONF1_DATLAT_DSEL_PHY_SHIFT = 26, DEFINE_BIT(DUMMY_RD_DQSG_DMYRD_EN, 22)
SHU_CONF1_DATLAT_DSEL_PHY_MASK = 0x7c000000, DEFINE_BIT(DUMMY_RD_SREF_DMYRD_EN, 21)
SHU_CONF1_DATLAT_DSEL_SHIFT = 8, DEFINE_BIT(DUMMY_RD_DUMMY_RD_EN, 20)
SHU_CONF1_DATLAT_DSEL_MASK = 0x00001f00, DEFINE_BIT(DUMMY_RD_DMY_RD_DBG, 7)
SHU_CONF1_DATLAT_SHIFT = 0, DEFINE_BIT(DUMMY_RD_DMY_WR_DBG, 6)
SHU_CONF1_DATLAT_MASK = 0x0000001f,
};
enum { DEFINE_BIT(STBCAL1_STBCNT_LATCH_EN, 11)
SHU_RANKCTL_RANKINCTL_PHY_SHIFT = 28, DEFINE_BIT(STBCAL1_STBENCMPEN, 10)
SHU_RANKCTL_RANKINCTL_PHY_MASK = 0xf0000000,
SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT = 24,
SHU_RANKCTL_RANKINCTL_ROOT1_MASK = 0x0f000000,
SHU_RANKCTL_RANKINCTL_SHIFT = 20,
SHU_RANKCTL_RANKINCTL_MASK = 0x00f00000,
};
enum { DEFINE_BITFIELD(SHU_ACTIM_XRT_XRTR2R, 3, 0)
SHU1_WODT_DBIWR_SHIFT = 29,
};
enum { DEFINE_BITFIELD(SHU_CONF1_DATLAT_DSEL_PHY, 30, 26)
SHURK_DQSCTL_DQSINCTL_SHIFT = 0, DEFINE_BITFIELD(SHU_CONF1_DATLAT_DSEL, 12, 8)
SHURK_DQSCTL_DQSINCTL_MASK = 0x0000000f, DEFINE_BITFIELD(SHU_CONF1_DATLAT, 4, 0)
};
enum { DEFINE_BIT(SHU_PIPE_READ_START_EXTEND1, 31)
SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT = 12, DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND1, 30)
SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT = 8, DEFINE_BIT(SHU_PIPE_READ_START_EXTEND2, 29)
SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT = 4, DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND2, 28)
SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT = 0, DEFINE_BIT(SHU_PIPE_READ_START_EXTEND3, 27)
}; DEFINE_BIT(SHU_PIPE_DLE_LAST_EXTEND3, 26)
enum { DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_PHY, 31, 28)
SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT = 12, DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24)
SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT = 8, DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20)
SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT = 4,
SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT = 0,
};
enum { DEFINE_BIT(SHU1_WODT_DBIWR, 29)
SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT = 12, DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0)
SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT = 8,
SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT = 4,
SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK = 0x00000070,
SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT = 0,
SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK = 0x00000007,
};
enum { DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12)
SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT = 12, DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4)
SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT = 8, DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0)
SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT = 4,
SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT = 0,
};
enum { DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12)
B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT = 16, DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4)
}; DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0)
enum { DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16)
B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT = 16, DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16)
};
enum { DEFINE_BIT(MISC_CTRL1_R_DMSTBENCMP_RK, 25)
MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT = 25, DEFINE_BIT(MISC_CTRL1_R_DMARPIDQ_SW, 7)
MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT = 7, DEFINE_BIT(MISC_CTRL1_R_DMPHYRST, 1)
MISC_CTRL1_R_DMPHYRST_SHIFT = 1,
};
enum { DEFINE_BITFIELD(MISC_STBERR_RK_R_STBERR_RK_R, 15, 0)
MISC_STBERR_RK_R_STBERR_RK_R_MASK = 0x0000ffff, DEFINE_BITFIELD(MISC_STBERR_RK_F_STBERR_RK_F, 15, 0)
};
enum { DEFINE_BITFIELD(SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0)
MISC_STBERR_RK_F_STBERR_RK_F_MASK = 0x0000ffff,
};
enum { DEFINE_BIT(SHU1_B0_DQ7_R_DMDQMDBI_SHU_B0, 7)
SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT = 0, DEFINE_BITFIELD(SHU1_B0_DQ7_R_DMRANKRXDVS, 3, 0)
SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK = 0x0000003f,
};
enum { DEFINE_BITFIELD(SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 14, 12)
SHU1_BX_DQ7_R_DMDQMDBI_SHIFT = 7,
SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT = 0,
SHU1_BX_DQ7_R_DMRANKRXDVS_MASK = 0x0000000f,
};
enum { DEFINE_BITFIELD(SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE, 11, 10)
SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_SHIFT = 12,
SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK = 0x00007000,
};
enum { DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_F_DLY_B0, 30, 24)
SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT = 10, DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, 22, 16)
SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK = 0x00000c00, DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_F_DLY_B0, 13, 8)
}; DEFINE_BITFIELD(SHU1_R0_B0_DQ6_RK0_RX_ARDQM0_R_DLY_B0, 5, 0)
enum { DEFINE_BITFIELD(FINE_TUNE_PBYTE, 29, 24)
SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK = 0x7f000000, DEFINE_BITFIELD(FINE_TUNE_DQM, 21, 16)
SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK = 0x007f0000, DEFINE_BITFIELD(FINE_TUNE_DQ, 13, 8)
SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK = 0x00003f00,
SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK = 0x0000003f,
};
enum { DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24)
FINE_TUNE_PBYTE_SHIFT = 24, DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8)
FINE_TUNE_PBYTE_MASK = 0x3f000000, DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0)
FINE_TUNE_DQM_SHIFT = 16,
FINE_TUNE_DQM_MASK = 0x003f0000,
FINE_TUNE_DQ_SHIFT = 8,
FINE_TUNE_DQ_MASK = 0x00003f00,
};
enum {
SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT = 24,
SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK = 0x3f000000,
SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK = 0x0000003f,
};
struct dramc_channel_regs { struct dramc_channel_regs {
union { union {