nb/amd/amdfam10: Get rid of device_t
Change-Id: Iac6be374842063cc383af20c73900e3699a72653 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -61,13 +61,13 @@
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struct amdfam10_sysconf_t sysconf;
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#define FX_DEVS NODE_NUMS
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static device_t __f0_dev[FX_DEVS];
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device_t __f1_dev[FX_DEVS];
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static device_t __f2_dev[FX_DEVS];
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static device_t __f4_dev[FX_DEVS];
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static struct device *__f0_dev[FX_DEVS];
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struct device *__f1_dev[FX_DEVS];
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static struct device *__f2_dev[FX_DEVS];
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static struct device *__f4_dev[FX_DEVS];
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static unsigned fx_devs = 0;
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device_t get_node_pci(u32 nodeid, u32 fn)
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struct device *get_node_pci(u32 nodeid, u32 fn)
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{
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#if NODE_NUMS + CONFIG_CDB >= 32
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if ((CONFIG_CDB + nodeid) < 32) {
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@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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if (fx_devs == 0)
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get_fx_devs();
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for (i = 0; i < fx_devs; i++) {
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device_t dev;
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struct device *dev;
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dev = __f1_dev[i];
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if (dev && dev->enabled) {
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pci_write_config32(dev, reg, value);
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@ -118,7 +118,7 @@ static void f1_write_config32(unsigned reg, u32 value)
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}
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}
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u32 amdfam10_nodeid(device_t dev)
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u32 amdfam10_nodeid(struct device *dev)
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{
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#if NODE_NUMS == 64
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unsigned busn;
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@ -188,7 +188,7 @@ static void ht_route_link(struct bus *link, scan_state mode)
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}
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}
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static void amd_g34_fixup(struct bus *link, device_t dev)
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static void amd_g34_fixup(struct bus *link, struct device *dev)
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{
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uint32_t nodeid = amdfam10_nodeid(dev);
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uint8_t rev_gte_d = 0;
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@ -316,7 +316,7 @@ static void trim_ht_chain(struct device *dev)
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}
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}
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static void amdfam10_scan_chains(device_t dev)
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static void amdfam10_scan_chains(struct device *dev)
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{
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struct bus *link;
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@ -373,7 +373,7 @@ static void amdfam10_scan_chains(device_t dev)
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}
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static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
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unsigned goal_link)
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{
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struct resource *res;
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@ -381,7 +381,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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int result;
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res = 0;
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for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
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device_t dev;
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struct device *dev;
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dev = __f0_dev[nodeid];
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if (!dev)
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continue;
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@ -401,7 +401,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
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return result;
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}
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static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link)
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static struct resource *amdfam10_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@ -434,7 +434,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi
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return resource;
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}
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static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link)
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static struct resource *amdfam10_find_mempair(struct device *dev, u32 nodeid, u32 link)
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{
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struct resource *resource;
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u32 free_reg, reg;
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@ -469,7 +469,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link
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}
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static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
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static void amdfam10_link_read_bases(struct device *dev, u32 nodeid, u32 link)
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{
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struct resource *resource;
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@ -510,7 +510,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
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}
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}
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static void amdfam10_read_resources(device_t dev)
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static void amdfam10_read_resources(struct device *dev)
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{
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u32 nodeid;
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struct bus *link;
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@ -522,7 +522,7 @@ static void amdfam10_read_resources(device_t dev)
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}
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}
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static void amdfam10_set_resource(device_t dev, struct resource *resource,
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static void amdfam10_set_resource(struct device *dev, struct resource *resource,
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u32 nodeid)
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{
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resource_t rbase, rend;
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@ -576,7 +576,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource,
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* but it is too difficult to deal with the resource allocation magic.
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*/
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static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
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static void amdfam10_create_vga_resource(struct device *dev, unsigned nodeid)
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{
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struct bus *link;
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struct resource *res;
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@ -586,7 +586,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
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for (link = dev->link_list; link; link = link->next) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
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extern device_t vga_pri; // the primary vga device, defined in device.c
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extern struct device *vga_pri; // the primary vga device, defined in device.c
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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/* We need to make sure the vga_pri is under the link */
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@ -617,7 +617,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
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amdfam10_set_resource(dev, res, nodeid);
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}
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static void amdfam10_set_resources(device_t dev)
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static void amdfam10_set_resources(struct device *dev)
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{
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unsigned nodeid;
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struct bus *bus;
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@ -695,7 +695,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = {
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.init = amdfam10_nb_init,
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};
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static void amdfam10_domain_read_resources(device_t dev)
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static void amdfam10_domain_read_resources(struct device *dev)
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{
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unsigned reg;
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uint8_t nvram;
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@ -710,7 +710,7 @@ static void amdfam10_domain_read_resources(device_t dev)
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/* Is this register allocated? */
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if ((base & 3) != 0) {
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unsigned nodeid, reg_link;
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device_t reg_dev;
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struct device *reg_dev;
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if (reg < 0xc0) { // mmio
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nodeid = (limit & 0xf) + (base&0x30);
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} else { // io
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@ -762,7 +762,7 @@ static void amdfam10_domain_read_resources(device_t dev)
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max_range = -1;
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interleaved = 0;
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max_range_limit = 0;
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device_t node_dev;
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struct device *node_dev;
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for (node = 0; node < FX_DEVS; node++) {
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node_dev = get_node_pci(node, 0);
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/* Test for node presence */
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@ -899,7 +899,7 @@ static void setup_uma_memory(void)
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#endif
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}
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static void amdfam10_domain_set_resources(device_t dev)
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static void amdfam10_domain_set_resources(struct device *dev)
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{
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unsigned long mmio_basek;
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u32 pci_tolm;
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@ -1000,7 +1000,7 @@ static void amdfam10_domain_set_resources(device_t dev)
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}
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}
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static void amdfam10_domain_scan_bus(device_t dev)
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static void amdfam10_domain_scan_bus(struct device *dev)
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{
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u32 reg;
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int i;
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@ -1021,7 +1021,7 @@ static void amdfam10_domain_scan_bus(device_t dev)
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*/
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get_fx_devs();
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for (i = 0; i < fx_devs; i++) {
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device_t f0_dev;
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struct device *f0_dev;
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f0_dev = __f0_dev[i];
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if (f0_dev && f0_dev->enabled) {
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u32 httc;
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@ -1299,7 +1299,7 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
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return len;
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}
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static int amdfam10_get_smbios_data(device_t dev, int *handle, unsigned long *current)
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static int amdfam10_get_smbios_data(struct device *dev, int *handle, unsigned long *current)
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{
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int len;
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int count = 0;
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@ -1334,7 +1334,7 @@ static struct device_operations pci_domain_ops = {
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#endif
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};
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static void sysconf_init(device_t dev) // first node
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static void sysconf_init(struct device *dev) // first node
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{
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sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
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sysconf.segbit = 0;
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@ -1376,7 +1376,7 @@ static void sysconf_init(device_t dev) // first node
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#endif
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}
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static void add_more_links(device_t dev, unsigned total_links)
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static void add_more_links(struct device *dev, unsigned total_links)
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{
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struct bus *link, *last = NULL;
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int link_num = -1;
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@ -1415,7 +1415,7 @@ static void add_more_links(device_t dev, unsigned total_links)
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static void remap_bsp_lapic(struct bus *cpu_bus)
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{
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struct device_path cpu_path;
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device_t cpu;
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struct device *cpu;
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u32 bsp_lapic_id = lapicid();
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if (bsp_lapic_id) {
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@ -1427,12 +1427,12 @@ static void remap_bsp_lapic(struct bus *cpu_bus)
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}
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}
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static void cpu_bus_scan(device_t dev)
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static void cpu_bus_scan(struct device *dev)
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{
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struct bus *cpu_bus;
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device_t dev_mc;
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struct device *dev_mc;
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#if CONFIG_CBB
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device_t pci_domain;
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struct device *pci_domain;
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#endif
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int nvram = 0;
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int i,j;
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@ -1535,7 +1535,7 @@ static void cpu_bus_scan(device_t dev)
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printk(BIOS_DEBUG, "Disabling siblings on each compute unit as requested\n");
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for (i = 0; i < nodes; i++) {
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device_t cdb_dev;
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struct device *cdb_dev;
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unsigned busn, devn;
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struct bus *pbus;
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@ -1668,14 +1668,14 @@ static void cpu_bus_scan(device_t dev)
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if (disable_cu_siblings && (j & 0x1))
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continue;
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device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
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if (cpu)
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amd_cpu_topology(cpu, i, j);
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}
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}
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}
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static void detect_and_enable_probe_filter(device_t dev)
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static void detect_and_enable_probe_filter(struct device *dev)
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{
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uint32_t dword;
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@ -1721,8 +1721,8 @@ static void detect_and_enable_probe_filter(device_t dev)
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/* Disable L3 and DRAM scrubbers and configure system for probe filter support */
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for (i = 0; i < sysconf.nodes; i++) {
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device_t f2x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 2));
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device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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struct device *f2x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 2));
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struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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f3x58[i] = pci_read_config32(f3x_dev, 0x58);
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f3x5c[i] = pci_read_config32(f3x_dev, 0x5c);
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@ -1791,7 +1791,7 @@ static void detect_and_enable_probe_filter(device_t dev)
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/* Enable probe filter */
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for (i = 0; i < sysconf.nodes; i++) {
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device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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dword = pci_read_config32(f3x_dev, 0x1c4);
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dword |= (0x1 << 31); /* L3TagInit = 1 */
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@ -1812,8 +1812,8 @@ static void detect_and_enable_probe_filter(device_t dev)
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/* Enable ATM mode */
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for (i = 0; i < sysconf.nodes; i++) {
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device_t f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
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device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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struct device *f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
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struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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dword = pci_read_config32(f0x_dev, 0x68);
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dword |= (0x1 << 12); /* ATMModeEn = 1 */
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@ -1829,7 +1829,7 @@ static void detect_and_enable_probe_filter(device_t dev)
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/* Reenable L3 and DRAM scrubbers */
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for (i = 0; i < sysconf.nodes; i++) {
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device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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pci_write_config32(f3x_dev, 0x58, f3x58[i]);
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pci_write_config32(f3x_dev, 0x5c, f3x5c[i]);
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@ -1838,7 +1838,7 @@ static void detect_and_enable_probe_filter(device_t dev)
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}
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}
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static void detect_and_enable_cache_partitioning(device_t dev)
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static void detect_and_enable_cache_partitioning(struct device *dev)
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{
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uint8_t i;
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uint32_t dword;
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@ -1865,9 +1865,9 @@ static void detect_and_enable_cache_partitioning(device_t dev)
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uint8_t dual_node = 0;
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for (i = 0; i < sysconf.nodes; i++) {
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device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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device_t f4x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 4));
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device_t f5x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 5));
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struct device *f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
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struct device *f4x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 4));
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struct device *f5x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 5));
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f3xe8 = pci_read_config32(f3x_dev, 0xe8);
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@ -1942,7 +1942,7 @@ static void detect_and_enable_cache_partitioning(device_t dev)
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}
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}
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static void cpu_bus_init(device_t dev)
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static void cpu_bus_init(struct device *dev)
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{
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detect_and_enable_probe_filter(dev);
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detect_and_enable_cache_partitioning(dev);
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