soc/marvell/armada38x: Add spi driver for armada38x
Port spi driver from uboot to coreboot BUG=chrome-os-partner:47462 TEST=None BRANCH=tot Change-Id: I747be7001f4cfb8eec33e8e5bdef3fe5bb0eb2ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbc5c2feb6ffacb54ed94e5c7b94b38be2b2ded Original-Change-Id: Ibea9a050ac8bdab6ce4eeb07accde53aeadade5f Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313340 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13111 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ruilin Hao
Patrick Georgi
parent
2c8b0b1373
commit
5b429ac2b2
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@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_MARVELL_ARMADA38X),y)
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bootblock-y += bootblock.c
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bootblock-y += bootblock_asm.S
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bootblock-y += spi.c
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bootblock-y += monotonic_timer.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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@ -9,11 +10,14 @@ endif
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verstage-$(CONFIG_DRIVERS_UART) += uart.c
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verstage-y += monotonic_timer.c
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verstage-y += spi.c
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romstage-y += spi.c
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romstage-y += cbmem.c
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romstage-y += monotonic_timer.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += spi.c
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ramstage-y += cbmem.c
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ramstage-y += monotonic_timer.c
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ramstage-y += soc.c
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@ -0,0 +1,488 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Marvell Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <delay.h>
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#include <spi_flash.h>
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include <console/console.h>
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#include <soc/common.h>
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/******************************************************************************
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base type define
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*******************************************************************************/
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#define MV_SPI_REG_READ mrvl_reg_read
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#define MV_SPI_REG_WRITE mrvl_reg_write
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#define MV_SPI_REG_BIT_SET mrvl_reg_bit_set
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#define MV_SPI_REG_BIT_RESET mrvl_reg_bit_reset
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#define MV_SPI_REGS_OFFSET(unit) (0x10600 + (unit * 0x80))
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#define MV_SPI_REGS_BASE(unit) (MV_SPI_REGS_OFFSET(unit))
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#define MV_SPI_IF_CONFIG_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x04)
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#define MV_SPI_SPR_OFFSET 0
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#define MV_SPI_SPR_MASK (0xF << MV_SPI_SPR_OFFSET)
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#define MV_SPI_SPPR_0_OFFSET 4
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#define MV_SPI_SPPR_0_MASK (0x1 << MV_SPI_SPPR_0_OFFSET)
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#define MV_SPI_SPPR_HI_OFFSET 6
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#define MV_SPI_SPPR_HI_MASK (0x3 << MV_SPI_SPPR_HI_OFFSET)
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#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */
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#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET)
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#define MV_SPI_IF_CTRL_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x00)
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#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */
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#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET)
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#define MV_SPI_CS_NUM_OFFSET 2
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#define MV_SPI_CS_NUM_MASK (0x7 << MV_SPI_CS_NUM_OFFSET)
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#define MV_SPI_CPOL_OFFSET 11
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#define MV_SPI_CPOL_MASK (0x1 << MV_SPI_CPOL_OFFSET)
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#define MV_SPI_CPHA_OFFSET 12
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#define MV_SPI_CPHA_MASK (0x1 << MV_SPI_CPHA_OFFSET)
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#define MV_SPI_TXLSBF_OFFSET 13
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#define MV_SPI_TXLSBF_MASK (0x1 << MV_SPI_TXLSBF_OFFSET)
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#define MV_SPI_RXLSBF_OFFSET 14
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#define MV_SPI_RXLSBF_MASK (0x1 << MV_SPI_RXLSBF_OFFSET)
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/* SPI transfer flags */
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#define SPI_XFER_BEGIN 0x01
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#define SPI_XFER_END 0x02
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#define MV_SPI_INT_CAUSE_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x10)
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#define MV_SPI_DATA_OUT_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x08)
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#define MV_SPI_WAIT_RDY_MAX_LOOP 100000
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#define MV_SPI_DATA_IN_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x0c)
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#define MV_SPI_TMNG_PARAMS_REG(spi_id) (MV_SPI_REGS_BASE(spi_id) + 0x18)
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#define MV_SPI_TMISO_SAMPLE_OFFSET 6
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#define MV_SPI_TMISO_SAMPLE_MASK (0x3 << MV_SPI_TMISO_SAMPLE_OFFSET)
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#define CONFIG_ENV_SPI_MAX_HZ 50000000
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#define CONFIG_SF_DEFAULT_SPEED CONFIG_ENV_SPI_MAX_HZ
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#define CMD_READ_ARRAY_FAST 0x0b
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/******************************************************************************
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base type define end
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*******************************************************************************/
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/******************************************************************************
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struct define
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*******************************************************************************/
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typedef enum {
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SPI_TYPE_FLASH = 0,
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SPI_TYPE_SLIC_ZARLINK_SILABS,
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SPI_TYPE_SLIC_LANTIQ,
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SPI_TYPE_SLIC_ZSI,
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SPI_TYPE_SLIC_ISI
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} MV_SPI_TYPE;
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typedef struct {
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unsigned short ctrl_model;
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unsigned int tclk;
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} MV_SPI_HAL_DATA;
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typedef struct {
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int clock_pol_low;
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enum { SPI_CLK_HALF_CYC, SPI_CLK_BEGIN_CYC } clock_phase;
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int tx_msb_first;
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int rx_msb_first;
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} MV_SPI_IF_PARAMS;
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typedef struct {
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/* Does this device support 16 bits access */
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int en16_bit;
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/* should we assert / disassert CS for each byte we read / write */
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int byte_cs_asrt;
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int clock_pol_low;
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unsigned int baud_rate;
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unsigned int clk_phase;
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} MV_SPI_TYPE_INFO;
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/******************************************************************************
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struct define end
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*******************************************************************************/
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/******************************************************************************
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param define
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*******************************************************************************/
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static MV_SPI_HAL_DATA spi_hal_data;
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static MV_SPI_TYPE_INFO *curr_spi_info = NULL;
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static MV_SPI_TYPE_INFO spi_types[] = { {.en16_bit = MV_TRUE,
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.clock_pol_low = MV_TRUE,
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.byte_cs_asrt = MV_FALSE,
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.baud_rate = (20 << 20), /* 20_m */
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.clk_phase = SPI_CLK_BEGIN_CYC},
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{.en16_bit = MV_FALSE,
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.clock_pol_low = MV_TRUE,
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.byte_cs_asrt = MV_TRUE,
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.baud_rate = 0x00800000,
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.clk_phase = SPI_CLK_BEGIN_CYC},
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{.en16_bit = MV_FALSE,
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.clock_pol_low = MV_TRUE,
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.byte_cs_asrt = MV_FALSE,
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.baud_rate = 0x00800000,
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.clk_phase = SPI_CLK_BEGIN_CYC},
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{.en16_bit = MV_FALSE,
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.clock_pol_low = MV_TRUE,
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.byte_cs_asrt = MV_TRUE,
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.baud_rate = 0x00800000,
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.clk_phase = SPI_CLK_HALF_CYC},
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{.en16_bit = MV_FALSE,
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.clock_pol_low = MV_FALSE,
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.byte_cs_asrt = MV_TRUE,
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.baud_rate = 0x00200000,
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.clk_phase = SPI_CLK_HALF_CYC} };
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/******************************************************************************
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param define end
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*******************************************************************************/
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static struct spi_slave s_spi;
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static int mv_spi_baud_rate_set(unsigned char spi_id,
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unsigned int serial_baud_rate);
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static void mv_spi_cs_deassert(unsigned char spi_id);
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static int mv_spi_cs_set(unsigned char spi_id, unsigned char cs_id);
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static int mv_spi_if_config_set(unsigned char spi_id,
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MV_SPI_IF_PARAMS *if_params);
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static int mv_spi_params_set(unsigned char spi_id,
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unsigned char cs_id,
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MV_SPI_TYPE type);
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static int mv_spi_init(unsigned char spi_id,
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unsigned char cs_id,
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unsigned int serial_baud_rate,
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MV_SPI_HAL_DATA *hal_data);
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static int mv_spi_sys_init(unsigned char spi_id,
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unsigned char cs_id,
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unsigned int serial_baud_rate);
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static void mv_spi_cs_assert(unsigned char spi_id);
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static int mv_spi_8bit_data_tx_rx(unsigned char spi_id,
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unsigned char tx_data,
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unsigned char *p_rx_data);
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int mv_spi_baud_rate_set(unsigned char spi_id, unsigned int serial_baud_rate)
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{
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unsigned int spr, sppr;
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unsigned int divider;
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unsigned int best_spr = 0, best_sppr = 0;
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unsigned char exact_match = 0;
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unsigned int min_baud_offset = 0xFFFFFFFF;
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unsigned int cpu_clk = spi_hal_data.tclk; /*mv_cpu_pclk_get();*/
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unsigned int temp_reg;
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assert(cpu_clk != serial_baud_rate);
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/* Find the best prescale configuration - less or equal */
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for (spr = 1; spr <= 15; spr++) {
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for (sppr = 0; sppr <= 7; sppr++) {
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divider = spr * (1 << sppr);
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/* check for higher - irrelevant */
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if ((cpu_clk / divider) > serial_baud_rate)
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continue;
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/* check for exact fit */
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if ((cpu_clk / divider) == serial_baud_rate) {
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best_spr = spr;
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best_sppr = sppr;
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exact_match = 1;
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break;
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}
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/* check if this is better than the previous one */
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if ((serial_baud_rate - (cpu_clk / divider)) <
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min_baud_offset) {
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min_baud_offset =
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serial_baud_rate - cpu_clk / divider;
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best_spr = spr;
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best_sppr = sppr;
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}
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}
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if (exact_match == 1)
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break;
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}
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if (best_spr == 0) {
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printk(BIOS_INFO, "%s ERROR: SPI baud rate prescale error!\n",
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__func__);
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return MV_OUT_OF_RANGE;
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}
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/* configure the Prescale */
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temp_reg = MV_SPI_REG_READ(MV_SPI_IF_CONFIG_REG(spi_id)) &
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~(MV_SPI_SPR_MASK | MV_SPI_SPPR_0_MASK | MV_SPI_SPPR_HI_MASK);
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temp_reg |= ((best_spr << MV_SPI_SPR_OFFSET) |
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((best_sppr & 0x1) << MV_SPI_SPPR_0_OFFSET) |
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((best_sppr >> 1) << MV_SPI_SPPR_HI_OFFSET));
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MV_SPI_REG_WRITE(MV_SPI_IF_CONFIG_REG(spi_id), temp_reg);
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return MV_OK;
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}
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void mv_spi_cs_deassert(unsigned char spi_id)
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{
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MV_SPI_REG_BIT_RESET(MV_SPI_IF_CTRL_REG(spi_id), MV_SPI_CS_ENABLE_MASK);
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}
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int mv_spi_cs_set(unsigned char spi_id, unsigned char cs_id)
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{
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unsigned int ctrl_reg;
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static unsigned char last_cs_id = 0xFF;
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static unsigned char last_spi_id = 0xFF;
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if (cs_id > 7)
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return MV_BAD_PARAM;
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if ((last_spi_id == spi_id) && (last_cs_id == cs_id))
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return MV_OK;
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ctrl_reg = MV_SPI_REG_READ(MV_SPI_IF_CTRL_REG(spi_id));
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ctrl_reg &= ~MV_SPI_CS_NUM_MASK;
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ctrl_reg |= (cs_id << MV_SPI_CS_NUM_OFFSET);
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MV_SPI_REG_WRITE(MV_SPI_IF_CTRL_REG(spi_id), ctrl_reg);
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last_spi_id = spi_id;
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last_cs_id = cs_id;
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return MV_OK;
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}
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int mv_spi_if_config_set(unsigned char spi_id, MV_SPI_IF_PARAMS *if_params)
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{
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unsigned int ctrl_reg;
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ctrl_reg = MV_SPI_REG_READ(MV_SPI_IF_CONFIG_REG(spi_id));
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/* Set Clock Polarity */
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ctrl_reg &= ~(MV_SPI_CPOL_MASK | MV_SPI_CPHA_MASK | MV_SPI_TXLSBF_MASK |
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MV_SPI_RXLSBF_MASK);
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if (if_params->clock_pol_low)
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ctrl_reg |= MV_SPI_CPOL_MASK;
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if (if_params->clock_phase == SPI_CLK_BEGIN_CYC)
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ctrl_reg |= MV_SPI_CPHA_MASK;
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if (if_params->tx_msb_first)
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ctrl_reg |= MV_SPI_TXLSBF_MASK;
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if (if_params->rx_msb_first)
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ctrl_reg |= MV_SPI_RXLSBF_MASK;
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MV_SPI_REG_WRITE(MV_SPI_IF_CONFIG_REG(spi_id), ctrl_reg);
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return MV_OK;
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}
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int mv_spi_params_set(unsigned char spi_id,
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unsigned char cs_id,
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MV_SPI_TYPE type)
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{
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MV_SPI_IF_PARAMS if_params;
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if (MV_OK != mv_spi_cs_set(spi_id, cs_id)) {
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printk(BIOS_INFO, "Error, setting SPI CS failed\n");
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return MV_ERROR;
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}
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if (curr_spi_info != (&(spi_types[type]))) {
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curr_spi_info = &(spi_types[type]);
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mv_spi_baud_rate_set(spi_id, curr_spi_info->baud_rate);
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if_params.clock_pol_low = curr_spi_info->clock_pol_low;
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if_params.clock_phase = curr_spi_info->clk_phase;
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if_params.tx_msb_first = MV_FALSE;
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if_params.rx_msb_first = MV_FALSE;
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mv_spi_if_config_set(spi_id, &if_params);
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}
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return MV_OK;
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}
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int mv_spi_init(unsigned char spi_id,
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unsigned char cs_id,
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unsigned int serial_baud_rate,
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MV_SPI_HAL_DATA *hal_data)
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{
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int ret;
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unsigned int timing_reg;
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spi_hal_data.ctrl_model = hal_data->ctrl_model;
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spi_hal_data.tclk = hal_data->tclk;
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/* Set the serial clock */
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ret = mv_spi_baud_rate_set(spi_id, serial_baud_rate);
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if (ret != MV_OK)
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return ret;
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/* Configure the default SPI mode to be 8bit */
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MV_SPI_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG(spi_id),
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MV_SPI_BYTE_LENGTH_MASK);
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timing_reg = MV_SPI_REG_READ(MV_SPI_TMNG_PARAMS_REG(spi_id));
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timing_reg &= ~MV_SPI_TMISO_SAMPLE_MASK;
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timing_reg |= (0x2) << MV_SPI_TMISO_SAMPLE_OFFSET;
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MV_SPI_REG_WRITE(MV_SPI_TMNG_PARAMS_REG(spi_id), timing_reg);
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/* Verify that the CS is deasserted */
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mv_spi_cs_deassert(spi_id);
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mv_spi_params_set(spi_id, cs_id, SPI_TYPE_FLASH);
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return MV_OK;
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}
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int mv_spi_sys_init(unsigned char spi_id,
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unsigned char cs_id,
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unsigned int serial_baud_rate)
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{
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MV_SPI_HAL_DATA hal_data;
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hal_data.ctrl_model = MV_6810_DEV_ID;
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hal_data.tclk = MV_BOARD_TCLK_250MHZ;
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return mv_spi_init(spi_id, cs_id, serial_baud_rate, &hal_data);
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}
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void mv_spi_cs_assert(unsigned char spi_id)
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{
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MV_SPI_REG_BIT_SET(MV_SPI_IF_CTRL_REG(spi_id), MV_SPI_CS_ENABLE_MASK);
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}
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int mv_spi_8bit_data_tx_rx(unsigned char spi_id,
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unsigned char tx_data,
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unsigned char *p_rx_data)
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{
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unsigned int i;
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int ready = MV_FALSE;
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if (curr_spi_info->byte_cs_asrt)
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mv_spi_cs_assert(spi_id);
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/* First clear the bit in the interrupt cause register */
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MV_SPI_REG_WRITE(MV_SPI_INT_CAUSE_REG(spi_id), 0x0);
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/* Transmit data */
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MV_SPI_REG_WRITE(MV_SPI_DATA_OUT_REG(spi_id), tx_data);
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/* wait with timeout for memory ready */
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for (i = 0; i < MV_SPI_WAIT_RDY_MAX_LOOP; i++) {
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if (MV_SPI_REG_READ(MV_SPI_INT_CAUSE_REG(spi_id))) {
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ready = MV_TRUE;
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break;
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}
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}
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|
||||
if (!ready) {
|
||||
if (curr_spi_info->byte_cs_asrt) {
|
||||
mv_spi_cs_deassert(spi_id);
|
||||
/* WA to compansate Zarlink SLIC CS off time */
|
||||
udelay(4);
|
||||
}
|
||||
return MV_TIMEOUT;
|
||||
}
|
||||
|
||||
/* check that the RX data is needed */
|
||||
if (p_rx_data)
|
||||
*p_rx_data = MV_SPI_REG_READ(MV_SPI_DATA_IN_REG(spi_id));
|
||||
|
||||
if (curr_spi_info->byte_cs_asrt) {
|
||||
mv_spi_cs_deassert(spi_id);
|
||||
/* WA to compansate Zarlink SLIC CS off time */
|
||||
udelay(4);
|
||||
}
|
||||
|
||||
return MV_OK;
|
||||
}
|
||||
|
||||
static int mrvl_spi_xfer(struct spi_slave *slave,
|
||||
unsigned int bitlen,
|
||||
const void *dout,
|
||||
void *din)
|
||||
{
|
||||
int ret;
|
||||
unsigned char *pdout = (unsigned char *)dout;
|
||||
unsigned char *pdin = (unsigned char *)din;
|
||||
int tmp_bitlen = bitlen;
|
||||
unsigned char tmp_dout = 0;
|
||||
|
||||
/* Verify that the SPI mode is in 8bit mode */
|
||||
MV_SPI_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG(slave->bus),
|
||||
MV_SPI_BYTE_LENGTH_MASK);
|
||||
|
||||
while (tmp_bitlen > 0) {
|
||||
if (pdout)
|
||||
tmp_dout = (*pdout) & 0xff;
|
||||
|
||||
/* Transmitted and wait for the transfer to be completed */
|
||||
ret = mv_spi_8bit_data_tx_rx(slave->bus, tmp_dout, pdin);
|
||||
if (ret != MV_OK)
|
||||
return ret;
|
||||
|
||||
/* increment the pointers */
|
||||
if (pdin)
|
||||
pdin++;
|
||||
if (pdout)
|
||||
pdout++;
|
||||
|
||||
tmp_bitlen -= 8;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
struct spi_slave *slave = &s_spi;
|
||||
|
||||
slave->bus = bus;
|
||||
slave->cs = cs;
|
||||
mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED);
|
||||
return slave;
|
||||
}
|
||||
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
mv_spi_cs_set(slave->bus, slave->cs);
|
||||
mv_spi_cs_assert(slave->bus);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
mv_spi_cs_deassert(slave->bus);
|
||||
}
|
||||
|
||||
unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
|
||||
{
|
||||
return buf_len;
|
||||
}
|
||||
|
||||
int spi_xfer(struct spi_slave *slave,
|
||||
const void *dout,
|
||||
unsigned out_bytes,
|
||||
void *din,
|
||||
unsigned in_bytes)
|
||||
{
|
||||
int ret = -1;
|
||||
|
||||
if (out_bytes)
|
||||
ret = mrvl_spi_xfer(slave, out_bytes * 8, dout, din);
|
||||
else if (in_bytes)
|
||||
ret = mrvl_spi_xfer(slave, in_bytes * 8, dout, din);
|
||||
else
|
||||
die("Unexpected condition in spi_xfer\n");
|
||||
return ret;
|
||||
}
|
||||
Loading…
Reference in New Issue