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mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED 

Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This commit is contained in:
Felix Held 2022-03-18 16:57:22 +01:00
parent b9ee6f351b
commit 5b51faaaea
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
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@ -47,6 +47,8 @@ chip soc/amd/sabrina
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
device domain 0 on device domain 0 on
device ref lpc_bridge on device ref lpc_bridge on
chip ec/google/chromeec chip ec/google/chromeec