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mb/google/hatch: Enable SATA for Hatch 

This patch enables the SATA for hatch,
* Enable the SATA port 1.
* Configure the GPIO for SATA.

BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.

Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30435
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya 2018-12-26 17:14:31 +05:30 committed by Subrata Banik
parent 581383aaed
commit 5c1f178075
2 changed files with 13 additions and 1 deletions
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8
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -39,6 +39,12 @@ chip soc/intel/cannonlake
# FSP configuration # FSP configuration
register "InternalGfx" = "1" register "InternalGfx" = "1"
register "SkipExtGfxScan" = "1" register "SkipExtGfxScan" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "satapwroptimize" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
@ -67,7 +73,7 @@ chip soc/intel/cannonlake
device pci 16.3 off end # Management Engine KT Redirection device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 off end # SATA device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4 device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5 device pci 19.1 off end # I2C #5
device pci 19.2 off end # UART #2 device pci 19.2 off end # UART #2

6
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -43,6 +43,12 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_C20, NONE, DEEP), PAD_CFG_GPI(GPP_C20, NONE, DEEP),
/* EC_IN_RW_OD */ /* EC_IN_RW_OD */
PAD_CFG_GPI(GPP_C22, NONE, DEEP), PAD_CFG_GPI(GPP_C22, NONE, DEEP),
/* SATAGP1 */
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
/* M2_SSD_PE_WAKE_ODL */
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
/* SATA_DEVSLP1 */
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
/* PCH_MEM_STRAP0 */ /* PCH_MEM_STRAP0 */
PAD_CFG_GPI(GPP_F20, NONE, PLTRST), PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
/* PCH_MEM_STRAP1 */ /* PCH_MEM_STRAP1 */