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mb/asus/p5qc/devicetree.cb: Drop zero values 

They default to zero already. Moreover, the comment about AHCI mode no
longer applies, as it was made the default mode.

Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-01-01 19:21:28 +01:00 committed by Nico Huber
parent d2f3afcc17
commit 5c74911f71
3 changed files with 3 additions and 12 deletions
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5
src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
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@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
# Set AHCI mode.
register "sata_port_map" = "0x3f"
register "sata_clock_request" = "0"
register "sata_traffic_monitor" = "0"
register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"

5
src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
View File

@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
# Set AHCI mode.
register "sata_port_map" = "0x3f"
register "sata_clock_request" = "0"
register "sata_traffic_monitor" = "0"
register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"

5
src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
View File

@ -37,10 +37,7 @@ chip northbridge/intel/x4x # Northbridge
chip southbridge/intel/i82801jx # Southbridge
register "gpe0_en" = "0x40"
# Set AHCI mode.
register "sata_port_map" = "0x3f"
register "sata_clock_request" = "0"
register "sata_traffic_monitor" = "0"
register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots.
register "pcie_slot_implemented" = "0x31"