mb/starlabs/lite/{glk,glkr}: Adjust THERMTRIP GPIO

Modify the configuration of GPIO_74 (PMIC Thermal Trip Point) as
in it's current configuration, it stops the laptop entering S5.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e31f095ff42a03e3ea1496fe67d69b0f1763a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2022-09-07 16:08:34 +01:00 committed by Felix Held
parent bc8f859b2d
commit 5d029bbb90
2 changed files with 4 additions and 2 deletions

View File

@ -169,7 +169,8 @@ const struct pad_config gpio_table[] = {
/* GPIO_73: Not Connected */ /* GPIO_73: Not Connected */
PAD_NC(GPIO_73, DN_20K), PAD_NC(GPIO_73, DN_20K),
/* GPIO_74: PMIC_THERMTRIP# */ /* GPIO_74: PMIC_THERMTRIP# */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), _PAD_CFG_STRUCT(GPIO_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
/* GPIO_75: PROCHOT#_CPU */ /* GPIO_75: PROCHOT#_CPU */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD),
/* GPIO_211: EMMC_RST#_CPU */ /* GPIO_211: EMMC_RST#_CPU */

View File

@ -169,7 +169,8 @@ const struct pad_config gpio_table[] = {
/* GPIO_73: WiFi Disable */ /* GPIO_73: WiFi Disable */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 1, DEEP, NONE, IGNORE, DISPUPD), PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 1, DEEP, NONE, IGNORE, DISPUPD),
/* GPIO_74: PMIC_THERMTRIP# */ /* GPIO_74: PMIC_THERMTRIP# */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), _PAD_CFG_STRUCT(GPIO_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF),
PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),
/* GPIO_75: PROCHOT#_CPU */ /* GPIO_75: PROCHOT#_CPU */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD),
/* GPIO_211: EMMC_RST#_CPU */ /* GPIO_211: EMMC_RST#_CPU */