GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX) 

This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).

Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Julius Werner 2019-03-07 17:07:26 -08:00 committed by Patrick Georgi
parent 2de19038be
commit 5d1f9a0096
31 changed files with 51 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/armv7/mmu.c
View File

@ -277,7 +277,7 @@ void mmu_init(void)
for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES) for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES)
table[0] = ATTR_UNUSED; table[0] = ATTR_UNUSED;
if (CONFIG_ARM_LPAE) { if (CONFIG(ARM_LPAE)) {
pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB); pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
pte_t *pmd = ttb_buff; pte_t *pmd = ttb_buff;
int i; int i;
@ -331,7 +331,7 @@ void mmu_init(void)
* See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
*/ */
write_ttbcr( write_ttbcr(
CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */ CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */
0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */
); );

6
src/arch/x86/failover.ld
View File

@ -28,7 +28,7 @@ SECTIONS
* boundary anyway, so no pad byte appears between _rom and _start. * boundary anyway, so no pad byte appears between _rom and _start.
*/ */
.bogus ROMLOC_MIN : { .bogus ROMLOC_MIN : {
. = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4);
ROMLOC = .; ROMLOC = .;
} >rom = 0xff } >rom = 0xff
@ -50,10 +50,10 @@ SECTIONS
* address gets applied. * address gets applied.
*/ */
ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
(CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
/* Post-check proper SIPI vector. */ /* Post-check proper SIPI vector. */
_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), _bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff),
"Address mismatch on AP_SIPI_VECTOR"); "Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : { /DISCARD/ : {

2
src/arch/x86/memlayout.ld
View File

@ -26,7 +26,7 @@ SECTIONS
* conditionalize with macros. * conditionalize with macros.
*/ */
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
RAMSTAGE(CONFIG_RAMBASE, (CONFIG_RELOCATABLE_RAMSTAGE ? 8M : RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M :
CONFIG_RAMTOP - CONFIG_RAMBASE)) CONFIG_RAMTOP - CONFIG_RAMBASE))
#elif ENV_ROMSTAGE #elif ENV_ROMSTAGE

6
src/commonlib/storage/sdhci.c
View File

@ -30,9 +30,9 @@
#include <timer.h> #include <timer.h>
#include <commonlib/stdlib.h> #include <commonlib/stdlib.h>
#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \ #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
|| (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \
|| (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \ || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \
|| ENV_POSTCAR || ENV_RAMSTAGE) || ENV_POSTCAR || ENV_RAMSTAGE)
__weak void *dma_malloc(size_t length_in_bytes) __weak void *dma_malloc(size_t length_in_bytes)

2
src/cpu/amd/family_10h-family_15h/fidvid.c
View File

@ -1084,7 +1084,7 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
} }
#else #else
for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv); for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv);
#endif #endif
print_debug_fv("common_fid = ", fv.common_fid); print_debug_fv("common_fid = ", fv.common_fid);

2
src/cpu/amd/quadcore/amd_sibling.c
View File

@ -74,7 +74,7 @@ u32 get_apicid_base(u32 ioapic_num)
u32 siblings; u32 siblings;
u32 nb_cfg_54; u32 nb_cfg_54;
u32 disable_siblings = !CONFIG_LOGICAL_CPUS; u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
get_option(&disable_siblings, "multi_core"); get_option(&disable_siblings, "multi_core");

2
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@ -24,7 +24,7 @@
#endif #endif
static int first_time = 1; static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS; static int disable_siblings = !CONFIG(LOGICAL_CPUS);
/* Return true if running thread does not have the smallest lapic ID /* Return true if running thread does not have the smallest lapic ID
* within a CPU core. * within a CPU core.

4
src/device/device.c
View File

@ -790,12 +790,12 @@ static void set_vga_bridge_bits(void)
if (!vga) if (!vga)
vga = vga_onboard; vga = vga_onboard;
if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && vga_onboard)
vga = vga_onboard; vga = vga_onboard;
/* If we prefer plugin VGA over chipset VGA, the chipset might /* If we prefer plugin VGA over chipset VGA, the chipset might
want to know. */ want to know. */
if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && if (!CONFIG(ONBOARD_VGA_IS_PRIMARY) && (vga != vga_onboard) &&
vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) {
printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n");
vga_onboard->ops->disable(vga_onboard); vga_onboard->ops->disable(vga_onboard);

4
src/drivers/intel/wifi/wifi.c
View File

@ -101,7 +101,7 @@ static void emit_sar_acpi_structures(void)
package_size = 1 + 1 + BYTES_PER_SAR_LIMIT; package_size = 1 + 1 + BYTES_PER_SAR_LIMIT;
acpigen_write_package(package_size); acpigen_write_package(package_size);
acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI); acpigen_write_dword(WRDS_DOMAIN_TYPE_WIFI);
acpigen_write_dword(CONFIG_SAR_ENABLE); acpigen_write_dword(CONFIG(SAR_ENABLE));
for (i = 0; i < BYTES_PER_SAR_LIMIT; i++) for (i = 0; i < BYTES_PER_SAR_LIMIT; i++)
acpigen_write_byte(sar_limits.sar_limit[0][i]); acpigen_write_byte(sar_limits.sar_limit[0][i]);
acpigen_pop_len(); acpigen_pop_len();
@ -130,7 +130,7 @@ static void emit_sar_acpi_structures(void)
package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT; package_size = 1 + 1 + 1 + (NUM_SAR_LIMITS - 1) * BYTES_PER_SAR_LIMIT;
acpigen_write_package(package_size); acpigen_write_package(package_size);
acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI); acpigen_write_dword(EWRD_DOMAIN_TYPE_WIFI);
acpigen_write_dword(CONFIG_DSAR_ENABLE); acpigen_write_dword(CONFIG(DSAR_ENABLE));
acpigen_write_dword(CONFIG_DSAR_SET_NUM); acpigen_write_dword(CONFIG_DSAR_SET_NUM);
for (i = 1; i < NUM_SAR_LIMITS; i++) for (i = 1; i < NUM_SAR_LIMITS; i++)
for (j = 0; j < BYTES_PER_SAR_LIMIT; j++) for (j = 0; j < BYTES_PER_SAR_LIMIT; j++)

2
src/drivers/pc80/pc/keyboard.c
View File

@ -249,7 +249,7 @@ uint8_t pc_keyboard_init(uint8_t probe_aux)
enum cb_err err; enum cb_err err;
uint8_t aux_dev_detected; uint8_t aux_dev_detected;
if (!CONFIG_DRIVERS_PS2_KEYBOARD) if (!CONFIG(DRIVERS_PS2_KEYBOARD))
return 0; return 0;
if (acpi_is_wakeup_s3()) if (acpi_is_wakeup_s3())

2
src/include/device/hypertransport_def.h
View File

@ -23,7 +23,7 @@ static inline bool offset_unit_id(bool is_sb_ht_chain)
{ {
bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
|| (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY return need_offset && (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY)
|| is_sb_ht_chain); || is_sb_ht_chain);
} }

2
src/include/device/i2c_simple.h
View File

@ -54,7 +54,7 @@ int i2c_write_field(unsigned int bus, uint8_t slave, uint8_t reg, uint8_t data,
static inline int i2c_transfer(unsigned int bus, struct i2c_msg *segments, static inline int i2c_transfer(unsigned int bus, struct i2c_msg *segments,
int count) int count)
{ {
if (CONFIG_SOFTWARE_I2C) if (CONFIG(SOFTWARE_I2C))
if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus]) if (bus < SOFTWARE_I2C_MAX_BUS && software_i2c[bus])
return software_i2c_transfer(bus, segments, count); return software_i2c_transfer(bus, segments, count);

2
src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
View File

@ -269,7 +269,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) { if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);

2
src/mainboard/amd/olivehillplus/BiosCallOuts.c
View File

@ -253,7 +253,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);

14
src/mainboard/amd/torpedo/gpio.c
View File

@ -340,7 +340,7 @@ void gpioEarlyInit(void) {
// //
// Enable/Disable OnBoard LAN // Enable/Disable OnBoard LAN
// //
if (!CONFIG_ONBOARD_LAN) if (!CONFIG(ONBOARD_LAN))
{ // 1 - DISABLED { // 1 - DISABLED
RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off
RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
@ -358,7 +358,7 @@ void gpioEarlyInit(void) {
// //
// Enable/Disable 1394 // Enable/Disable 1394
// //
if (!CONFIG_ONBOARD_1394) if (!CONFIG(ONBOARD_1394))
{ // 1 - DISABLED { // 1 - DISABLED
// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW
RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off
@ -387,7 +387,7 @@ void gpioEarlyInit(void) {
// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
// if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
// disable Onboard NEC USB3.0 controller // disable Onboard NEC USB3.0 controller
if (!CONFIG_ONBOARD_USB30) { if (!CONFIG(ONBOARD_USB30)) {
RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE
@ -401,7 +401,7 @@ void gpioEarlyInit(void) {
// amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO07: BT_ON, 0 - OFF, 1 - ON // GPIO07: BT_ON, 0 - OFF, 1 - ON
// //
if (!CONFIG_ONBOARD_BLUETOOTH) { if (!CONFIG(ONBOARD_BLUETOOTH)) {
//- if (SystemConfiguration.amdBlueTooth == 1) { //- if (SystemConfiguration.amdBlueTooth == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
//- } //- }
@ -412,7 +412,7 @@ void gpioEarlyInit(void) {
// amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
// //
if (!CONFIG_ONBOARD_WEBCAM) { if (!CONFIG(ONBOARD_WEBCAM)) {
//- if (SystemConfiguration.amdWebCam == 1) { //- if (SystemConfiguration.amdWebCam == 1) {
RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
//- } //- }
@ -423,7 +423,7 @@ void gpioEarlyInit(void) {
// amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
// //
if (!CONFIG_ONBOARD_TRAVIS) { if (!CONFIG(ONBOARD_TRAVIS)) {
//- if (SystemConfiguration.amdTravisCtrl == 0) { //- if (SystemConfiguration.amdTravisCtrl == 0) {
RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
//- } //- }
@ -432,7 +432,7 @@ void gpioEarlyInit(void) {
// //
// Disable Light Sensor if needed // Disable Light Sensor if needed
// //
if (CONFIG_ONBOARD_LIGHTSENSOR) { if (CONFIG(ONBOARD_LIGHTSENSOR)) {
//- if (SystemConfiguration.amdLightSensor == 1) { //- if (SystemConfiguration.amdLightSensor == 1) {
RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
//- } //- }

2
src/mainboard/bap/ode_e21XX/BiosCallOuts.c
View File

@ -255,7 +255,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);

12
src/mainboard/pcengines/apu1/mainboard.c
View File

@ -139,16 +139,16 @@ static void config_gpio_mux(void)
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
if (uart) if (uart)
uart->enabled = CONFIG_APU1_PINMUX_UART_C; uart->enabled = CONFIG(APU1_PINMUX_UART_C);
if (gpio) if (gpio)
gpio->enabled = CONFIG_APU1_PINMUX_GPIO0; gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
if (uart) if (uart)
uart->enabled = CONFIG_APU1_PINMUX_UART_D; uart->enabled = CONFIG(APU1_PINMUX_UART_D);
if (gpio) if (gpio)
gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; gpio->enabled = CONFIG(APU1_PINMUX_GPIO1);
} }
static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
@ -165,11 +165,11 @@ static void config_addon_uart(void)
struct device *uart; struct device *uart;
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
if (uart && uart->enabled && CONFIG_UART_C_RS485) if (uart && uart->enabled && CONFIG(UART_C_RS485))
pnp_raw_resource(uart, 0xf2, 0x12); pnp_raw_resource(uart, 0xf2, 0x12);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
if (uart && uart->enabled && CONFIG_UART_D_RS485) if (uart && uart->enabled && CONFIG(UART_D_RS485))
pnp_raw_resource(uart, 0xf2, 0x12); pnp_raw_resource(uart, 0xf2, 0x12);
} }

2
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -69,7 +69,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE; FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams->FchReset.SataEnable = hudson_sata_enable(); FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable(); FchParams->FchReset.IdeEnable = hudson_ide_enable();
FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);

4
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -177,7 +177,7 @@ static void ht_route_link(struct bus *link, scan_state mode)
pci_write_config32(link->dev, link->cap + 0x14, busses); pci_write_config32(link->dev, link->cap + 0x14, busses);
if (mode == HT_ROUTE_FINAL) { if (mode == HT_ROUTE_FINAL) {
if (CONFIG_HT_CHAIN_DISTRIBUTE) if (CONFIG(HT_CHAIN_DISTRIBUTE))
parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1; parent->subordinate = ALIGN_UP(link->subordinate, 8) - 1;
else else
parent->subordinate = link->subordinate; parent->subordinate = link->subordinate;
@ -1450,7 +1450,7 @@ static void cpu_bus_scan(struct device *dev)
siblings = 3; //quad core siblings = 3; //quad core
} }
disable_siblings = !CONFIG_LOGICAL_CPUS; disable_siblings = !CONFIG(LOGICAL_CPUS);
#if CONFIG(LOGICAL_CPUS) #if CONFIG(LOGICAL_CPUS)
get_option(&disable_siblings, "multi_core"); get_option(&disable_siblings, "multi_core");
#endif #endif

2
src/northbridge/amd/pi/agesawrapper.c
View File

@ -127,7 +127,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
// Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow
// the compiler to flag the error if CONFIG_GFXUMA is not set. // the compiler to flag the error if CONFIG_GFXUMA is not set.
PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (UINT16) PostParams->MemConfig.BottomIo = (UINT16)
(CONFIG_BOTTOMIO_POSITION >> 24); (CONFIG_BOTTOMIO_POSITION >> 24);

4
src/northbridge/intel/i945/gma.c
View File

@ -677,10 +677,10 @@ static void gma_ngi(struct device *const dev)
if (err == 0) if (err == 0)
gfx_set_init_done(1); gfx_set_init_done(1);
/* Linux relies on VBT for panel info. */ /* Linux relies on VBT for panel info. */
if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA"); generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA");
} }
if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G"); generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G");
} }
} }

2
src/northbridge/intel/i945/raminit.c
View File

@ -284,7 +284,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
/* clear self refresh status if check is disabled or not a resume */ /* clear self refresh status if check is disabled or not a resume */
if (!CONFIG_CHECK_SLFRCS_ON_RESUME if (!CONFIG(CHECK_SLFRCS_ON_RESUME)
|| sysinfo->boot_path != BOOT_PATH_RESUME) { || sysinfo->boot_path != BOOT_PATH_RESUME) {
MCHBAR8(SLFRCS) |= 3; MCHBAR8(SLFRCS) |= 3;
} else { } else {

2
src/northbridge/intel/sandybridge/romstage.c
View File

@ -67,7 +67,7 @@ void mainboard_romstage_entry(unsigned long bist)
mainboard_config_superio(); mainboard_config_superio();
/* USB is initialized in MRC if MRC is used. */ /* USB is initialized in MRC if MRC is used. */
if (CONFIG_USE_NATIVE_RAMINIT) { if (CONFIG(USE_NATIVE_RAMINIT)) {
early_usb_init(mainboard_usb_ports); early_usb_init(mainboard_usb_ports);
} }

2
src/soc/amd/common/block/pi/agesawrapper.c
View File

@ -180,7 +180,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct); AMD_POST_PARAMS *PostParams = create_struct(&AmdParamStruct);
PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE;
PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.UmaSize = 0;
PostParams->MemConfig.BottomIo = (uint16_t) PostParams->MemConfig.BottomIo = (uint16_t)
(CONFIG_BOTTOMIO_POSITION >> 24); (CONFIG_BOTTOMIO_POSITION >> 24);

2
src/soc/nvidia/tegra124/bootblock.c
View File

@ -64,7 +64,7 @@ void main(void)
pinmux_set_config(PINMUX_UART2_RTS_N_INDEX, pinmux_set_config(PINMUX_UART2_RTS_N_INDEX,
PINMUX_UART2_RTS_N_FUNC_UB3); PINMUX_UART2_RTS_N_FUNC_UB3);
if (CONFIG_BOOTBLOCK_CONSOLE) { if (CONFIG(BOOTBLOCK_CONSOLE)) {
console_init(); console_init();
exception_init(); exception_init();
} }

2
src/soc/nvidia/tegra210/bootblock.c
View File

@ -177,7 +177,7 @@ void main(void)
bootblock_mainboard_early_init(); bootblock_mainboard_early_init();
if (CONFIG_BOOTBLOCK_CONSOLE) { if (CONFIG(BOOTBLOCK_CONSOLE)) {
console_init(); console_init();
exception_init(); exception_init();
printk(BIOS_INFO, "T210: Bootblock here\n"); printk(BIOS_INFO, "T210: Bootblock here\n");

2
src/southbridge/amd/cimx/sb800/cfg.c
View File

@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
#endif #endif
/* LPC */ /* LPC */
/* SuperIO hardware monitor register access */ /* SuperIO hardware monitor register access */
sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM; sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/* /*
* GPP. default configure only enable port0 with 4 lanes, * GPP. default configure only enable port0 with 4 lanes,

2
src/southbridge/amd/cimx/sb900/early.c
View File

@ -40,7 +40,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6); outb(0xEA, 0xCD6);
data = inb(0xCD7); data = inb(0xCD7);
data &= !BIT0; data &= !BIT0;
if (!CONFIG_PCIB_ENABLE) { if (!CONFIG(PCIB_ENABLE)) {
data |= BIT0; data |= BIT0;
} }
outb(data, 0xCD7); outb(data, 0xCD7);

2
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -418,7 +418,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void) static void pch_set_acpi_mode(void)
{ {
if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT #if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode

2
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -433,7 +433,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void) static void pch_set_acpi_mode(void)
{ {
if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT #if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode

2
src/southbridge/nvidia/ck804/ck804.h
View File

@ -24,7 +24,7 @@
#endif #endif
#define CK804B_BUSN 0x80 #define CK804B_BUSN 0x80
#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1) #define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
#ifdef __PRE_RAM__ #ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);