add cs5536
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
05c0869fac
commit
5d69896c87
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#config chip.h
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driver cs5536.o
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#driver cs5535_pci.o
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#driver cs5535_ide.o
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@ -0,0 +1,10 @@
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#ifndef _SOUTHBRIDGE_AMD_CS5536
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#define _SOUTHBRIDGE_AMD_CS5536
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extern struct chip_operations southbridge_amd_cs5536_ops;
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struct southbridge_amd_cs5536_config {
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int none;
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};
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#endif /* _SOUTHBRIDGE_AMD_CS5536 */
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@ -0,0 +1,41 @@
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include "cs5536.h"
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static void southbridge_init(struct device *dev)
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{
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printk_err("cs5536: %s\n", __FUNCTION__);
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setup_i8259();
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}
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static void southbridge_enable(struct device *dev)
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{
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printk_err("%s: dev is %p\n", __FUNCTION__, dev);
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}
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static void cs5536_pci_dev_enable_resources(device_t dev)
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{
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printk_err("cs5536.c: %s()\n", __FUNCTION__);
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pci_dev_enable_resources(dev);
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enable_childrens_resources(dev);
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}
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static struct device_operations southbridge_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = cs5536_pci_dev_enable_resources,
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.init = southbridge_init,
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.enable = southbridge_enable,
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.scan_bus = scan_static_bus,
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};
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static struct pci_driver cs5535_pci_driver __pci_driver = {
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.ops = &southbridge_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_CS5536_ISA
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};
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@ -0,0 +1,4 @@
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#ifndef _CS5535_H
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#define _CS5535_H
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#endif
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@ -0,0 +1,182 @@
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/*
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*
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* cs5536_early_setup.c: Early chipset initialization for CS5536 companion device
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*
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*
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* This file implements the initialization sequence documented in section 4.2 of
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* AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
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*
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*/
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#define CS5536_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5536 */
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#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
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/**
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* @brief Setup PCI IDSEL for CS5536
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*
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*
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*/
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static void cs5536_setup_extmsr(void)
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{
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msr_t msr;
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/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
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msr.hi = msr.lo = 0x00000000;
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if (CS5536_GLINK_PORT_NUM <= 4) {
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msr.lo = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 1) * 8);
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} else {
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msr.hi = CS5536_DEV_NUM << ((CS5536_GLINK_PORT_NUM - 5) * 8);
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}
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wrmsr(0x5000201e, msr);
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}
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static void cs5536_setup_idsel(void)
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{
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/* write IDSEL to the write once register at address 0x0000 */
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outl(0x1 << (CS5536_DEV_NUM + 10), 0);
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}
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static void cs5536_usb_swapsif(void)
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{
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msr_t msr;
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msr = rdmsr(0x51600005);
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//USB Serial short detect bit.
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if (msr.hi & 0x10) {
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/* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
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* SERSHRT error bit */
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msr.hi &= 0xFFFFFFFB;
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wrmsr(0x51600005, msr);
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}
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}
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static int cs5536_setup_iobase(void)
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{
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msr_t msr;
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/* setup LBAR for SMBus controller */
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__builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
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/* setup LBAR for GPIO */
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__builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
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/* setup LBAR for MFGPT */
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__builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
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/* setup LBAR for ACPI */
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__builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
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/* setup LBAR for PM Support */
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__builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
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}
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static void cs5536_setup_power_bottun(void)
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{
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/* not implemented yet */
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#if 0
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pwrBtn_setup:
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;
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; Power Button Setup
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;
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;mov eax, 0C0020000h ; 4 seconds + lock
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mov eax, 040020000h ; 4 seconds no lock
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mov dx, PMLogic_BASE + 40h
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out dx, eax
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; setup GPIO24, it is the external signal for 5536 vsb_work_aux
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; which controls all voltage rails except Vstandby & Vmem.
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; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
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; If GPIO24 is not enabled then soft-off will not work.
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mov dx, GPIOH_OUT_AUX1_SELECT
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mov eax, GPIOH_24_SET
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out dx, eax
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mov dx, GPIOH_OUTPUT_ENABLE
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out dx, eax
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#endif
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}
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static void cs5536_setup_gpio(void)
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{
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uint32_t val;
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/* setup GPIO pins 14/15 for SDA/SCL */
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val = (1<<14 | 1<<15);
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/* Output Enable */
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outl(0x3fffc000, 0x6100 + 0x04);
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//outl(val, 0x6100 + 0x04);
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/* Output AUX1 */
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outl(0x3fffc000, 0x6100 + 0x10);
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//outl(val, 0x6100 + 0x10);
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/* Input Enable */
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//outl(0x0f5af0a5, 0x6100 + 0x20);
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outl(0x3fffc000, 0x6100 + 0x20);
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//outl(val, 0x6100 + 0x20);
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/* Input AUX1 */
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//outl(0x3ffbc004, 0x6100 + 0x34);
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outl(0x3fffc000, 0x6100 + 0x34);
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//outl(val, 0x6100 + 0x34);
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}
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static void cs5536_disable_internal_uart(void)
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{
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/* not implemented yet */
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#if 0
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; The UARTs default to enabled.
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; Disable and reset them and configure them later. (SIO init)
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mov ecx, MDD_UART1_CONF
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RDMSR
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mov eax, 1h ; reset
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WRMSR
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mov eax, 0h ; disabled
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WRMSR
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mov ecx, MDD_UART2_CONF
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RDMSR
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mov eax, 1h ; reset
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WRMSR
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mov eax, 0h ; disabled
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WRMSR
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#endif
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}
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static void cs5536_setup_cis_mode(void)
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{
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msr_t msr;
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/* setup CPU interface serial to mode C on both sides */
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msr = __builtin_rdmsr(0x51000010);
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msr.lo &= ~0x18;
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msr.lo |= 0x10;
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__builtin_wrmsr(0x51000010, msr.lo, msr.hi);
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//Only do this if we are building for 5536
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__builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
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}
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static void dummy(void)
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{
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}
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static int cs5536_early_setup(void)
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{
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msr_t msr;
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cs5536_setup_extmsr();
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msr = rdmsr(GLCP_SYS_RSTPLL);
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if (msr.lo & (0x3f << 26)) {
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/* PLL is already set and we are reboot from PLL reset */
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print_debug("reboot from BIOS reset\n\r");
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return;
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}
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print_debug("Setup idsel\r\n");
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cs5536_setup_idsel();
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print_debug("Setup iobase\r\n");
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cs5536_usb_swapsif();
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cs5536_setup_iobase();
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print_debug("Setup gpio\r\n");
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cs5536_setup_gpio();
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print_debug("Setup cis_mode\r\n");
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cs5536_setup_cis_mode();
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print_debug("Setup smbus\r\n");
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cs5536_enable_smbus();
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dummy();
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}
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@ -0,0 +1,45 @@
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#include "cs5536_smbus.h"
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#define SMBUS_IO_BASE 0x6000
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/* initialization for SMBus Controller */
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static int cs5536_enable_smbus(void)
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{
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unsigned char val;
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/* reset SMBUS controller */
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outb(0, SMBUS_IO_BASE + SMB_CTRL2);
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/* Set SCL freq and enable SMB controller */
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val = inb(SMBUS_IO_BASE + SMB_CTRL2);
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val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);
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outb(val, SMBUS_IO_BASE + SMB_CTRL2);
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/* Setup SMBus host controller address to 0xEF */
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val = inb(SMBUS_IO_BASE + SMB_ADD);
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val |= (0xEF | SMB_ADD_SAEN);
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outb(val, SMBUS_IO_BASE + SMB_ADD);
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
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}
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#if 0
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static int smbus_recv_byte(unsigned device)
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{
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return do_smbus_recv_byte(SMBUS_IO_BASE, device);
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}
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static int smbus_send_byte(unsigned device, unsigned char val)
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{
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return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
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}
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static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
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{
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return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
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}
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#endif
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@ -0,0 +1,30 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "cs5535.h"
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static void ide_init(struct device *dev)
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{
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printk_spew("cs5535_ide: %s\n", __FUNCTION__);
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}
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static void ide_enable(struct device *dev)
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{
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printk_spew("cs5535_ide: %s\n", __FUNCTION__);
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.enable = ide_enable,
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};
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static struct pci_driver ide_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_NS,
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.device = PCI_DEVICE_ID_NS_CS5535_IDE,
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};
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//#include <device/smbus_def.h>
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#define SMBUS_ERROR -1
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#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
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#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
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#define SMB_SDA 0x00
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#define SMB_STS 0x01
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#define SMB_CTRL_STS 0x02
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#define SMB_CTRL1 0x03
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#define SMB_ADD 0x04
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#define SMB_CTRL2 0x05
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#define SMB_CTRL3 0x06
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#define SMB_STS_SLVSTP (0x01 << 7)
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#define SMB_STS_SDAST (0x01 << 6)
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#define SMB_STS_BER (0x01 << 5)
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#define SMB_STS_NEGACK (0x01 << 4)
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#define SMB_STS_STASTR (0x01 << 3)
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#define SMB_STS_NMATCH (0x01 << 2)
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#define SMB_STS_MASTER (0x01 << 1)
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#define SMB_STS_XMIT (0x01 << 0)
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#define SMB_CSTS_TGSCL (0x01 << 5)
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#define SMB_CSTS_TSDA (0x01 << 4)
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#define SMB_CSTS_GCMTCH (0x01 << 3)
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#define SMB_CSTS_MATCH (0x01 << 2)
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#define SMB_CSTS_BB (0x01 << 1)
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#define SMB_CSTS_BUSY (0x01 << 0)
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#define SMB_CTRL1_STASTRE (0x01 << 7)
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#define SMB_CTRL1_NMINTE (0x01 << 6)
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#define SMB_CTRL1_GCMEN (0x01 << 5)
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#define SMB_CTRL1_ACK (0x01 << 4)
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#define SMB_CTRL1_RSVD (0x01 << 3)
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#define SMB_CTRL1_INTEN (0x01 << 2)
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#define SMB_CTRL1_STOP (0x01 << 1)
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#define SMB_CTRL1_START (0x01 << 0)
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#define SMB_ADD_SAEN (0x01 << 7)
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#define SMB_CTRL2_ENABLE 0x01
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#define SMBUS_TIMEOUT (100*1000*10)
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#define SMBUS_STATUS_MASK 0xfbff
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#define SMBUS_IO_BASE 0x6000
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static void smbus_delay(void)
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{
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outb(0x80, 0x80);
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}
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/* generate a smbus start condition */
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static int smbus_start_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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/* issue a START condition */
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
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/* check for bus conflict */
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val = inb(smbus_io_base + SMB_STS);
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if ((val & SMB_STS_BER) != 0)
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return SMBUS_ERROR;
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/* check for SDA status */
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do {
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smbus_delay();
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val = inw(smbus_io_base + SMB_STS);
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if ((val & SMB_STS_SDAST) != 0) {
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break;
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}
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} while(--loops);
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int smbus_check_stop_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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/* check for SDA status */
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do {
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smbus_delay();
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val = inw(smbus_io_base + SMB_CTRL1);
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if ((val & SMB_CTRL1_STOP) == 0) {
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break;
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}
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} while(--loops);
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int smbus_stop_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
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}
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static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
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{
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unsigned char val;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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/* send the slave address */
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outb(device, smbus_io_base + SMB_SDA);
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/* check for bus conflict and NACK */
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val = inb(smbus_io_base + SMB_STS);
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if (((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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return SMBUS_ERROR;
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/* check for SDA status */
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do {
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smbus_delay();
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val = inw(smbus_io_base + SMB_STS);
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if ((val & SMB_STS_SDAST) != 0) {
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break;
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}
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} while(--loops);
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
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{
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unsigned char val;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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/* send the command */
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outb(command, smbus_io_base + SMB_SDA);
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/* check for bus conflict and NACK */
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val = inb(smbus_io_base + SMB_STS);
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if (((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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return SMBUS_ERROR;
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/* check for SDA status */
|
||||
do {
|
||||
smbus_delay();
|
||||
val = inw(smbus_io_base + SMB_STS);
|
||||
if ((val & SMB_STS_SDAST) != 0) {
|
||||
break;
|
||||
}
|
||||
} while(--loops);
|
||||
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
}
|
||||
|
||||
static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
|
||||
{
|
||||
unsigned char val, val1;
|
||||
|
||||
smbus_check_stop_condition(smbus_io_base);
|
||||
|
||||
smbus_start_condition(smbus_io_base);
|
||||
|
||||
smbus_send_slave_address(smbus_io_base, device);
|
||||
|
||||
smbus_send_command(smbus_io_base, address);
|
||||
|
||||
smbus_start_condition(smbus_io_base);
|
||||
|
||||
smbus_send_slave_address(smbus_io_base, device | 0x01);
|
||||
|
||||
/* send NACK to slave */
|
||||
val = inb(smbus_io_base + SMB_CTRL1);
|
||||
outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
|
||||
|
||||
val = inb(smbus_io_base + SMB_SDA);
|
||||
|
||||
//smbus_stop_condition(smbus_io_base);
|
||||
|
||||
return val;
|
||||
}
|
||||
Loading…
Reference in New Issue