GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/haswell/northbridge.c: Correct DPR handling 

DPR size is in MiB, but the range boundaries are expressed in KiB. In
addition, DPR and TSEG use the same attributes, so unify both regions.
Also improve a comment about DPR, since `is special` is uninformative.

Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-29 21:18:14 +01:00 committed by Patrick Georgi
parent 3d35756d5a
commit 5d7c3a4f01
1 changed files with 11 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/northbridge/intel/haswell/northbridge.c
View File

@ -251,7 +251,12 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
mc_read_map_entries(dev, &mc_values[0]); mc_read_map_entries(dev, &mc_values[0]);
mc_report_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]);
/* The DPR register is special */ /*
* DMA Protected Range can be reserved below TSEG for PCODE patch
* or TXT/BootGuard related data. Rather than report a base address,
* the DPR register reports the TOP of the region, which is the same
* as TSEG base. The region size is reported in MiB in bits 11:4.
*/
const union dpr_register dpr = { const union dpr_register dpr = {
.raw = pci_read_config32(dev, DPR), .raw = pci_read_config32(dev, DPR),
}; };
@ -290,23 +295,15 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
size_k = (0xa0000 >> 10) - base_k; size_k = (0xa0000 >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k); ram_resource(dev, index++, base_k, size_k);
/* 0xc0000 -> DPR base */ /* 0xc0000 -> TSEG - DPR */
base_k = 0xc0000 >> 10; base_k = 0xc0000 >> 10;
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - (base_k + dpr.size); size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
size_k -= dpr.size >> 10;
ram_resource(dev, index++, base_k, size_k); ram_resource(dev, index++, base_k, size_k);
/* DPR base -> TSEG */ /* TSEG - DPR -> BGSM */
if (dpr.size) {
resource = new_resource(dev, index++); resource = new_resource(dev, index++);
resource->base = (dpr.top - dpr.size) * MiB; resource->base = mc_values[TSEG_REG] - dpr.size;
resource->size = dpr.size * MiB;
resource->flags = IORESOURCE_MEM | IORESOURCE_STORED | IORESOURCE_CACHEABLE |
IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
/* TSEG -> BGSM */
resource = new_resource(dev, index++);
resource->base = mc_values[TSEG_REG];
resource->size = mc_values[BGSM_REG] - resource->base; resource->size = mc_values[BGSM_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;